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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
BINARY LOGIC
LOGIC GATES
BOOLEAN ALGEBRA LAWS
CONSENSUS THEOREM
DIFFERENT FORS OF BOOLEAN EQUATIONS
RELATION B/W MAX & MIN TERMS
16 type of LOGIC FUNCTIONS
AND & OR GATE
Other GATES
XOR & XNOR gates
NEGATED & COMPLIMENTRY GATES
TRISTATE gates & DIP
Illustration of NEGATIVE & POSITIVE LOGIC
Relation B/W XOR & XNOR gates
UNIVERSAL GATES
Implementation of XOR using minimum gates
Implementation of XNOR using minimum gates
Different levels of CIRCUIT
Special Characteristics of an IC
QUESTIONS
Q1 (Timing Diagram)
Q2 (Timing Diagram)
Q3 (Timing Diagram - DIfferent units)
Q4 (Timing Diagram)
Q5 (Output of Series of NOR gate )
Q6 (Output of combination of XOR )
Q7 (Circuit of NAND gates & diff delays)
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
TIMING CIRCUITS

 

 

Q- Implement 2 variable XOR gate using NAND only in minimum number of gates.

F= x XOR y = x’y+xy’ = x’y+xy’+xx’+yy’ = (x+y) (x’+y’)

Now we need to implement this circuit using NAND gates

F= (x+y)(xy)’ = x. (xy)’ + y. (xy)’

Take compliment

F’= ( x. (xy)’ + y. (xy)’ )’ = (x. (xy)’)’. (y. (xy)’)

Take compliment again

F=( (x. (xy)’)’. (y. (xy)’) )’

Now we can implement this using NAND gates

So we get that we need minimum of 4 NAND gates to implement XOR gate and if we are to implement XNOR gate then we’ll use 5 NAND gates with 5th gate used as inverter and placed in-front of 4th NAND gate in above circuit.

 

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