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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
BINARY LOGIC
LOGIC GATES
BOOLEAN ALGEBRA LAWS
CONSENSUS THEOREM
DIFFERENT FORS OF BOOLEAN EQUATIONS
RELATION B/W MAX & MIN TERMS
16 type of LOGIC FUNCTIONS
AND & OR GATE
Other GATES
XOR & XNOR gates
NEGATED & COMPLIMENTRY GATES
TRISTATE gates & DIP
Illustration of NEGATIVE & POSITIVE LOGIC
Relation B/W XOR & XNOR gates
UNIVERSAL GATES
Implementation of XOR using minimum gates
Implementation of XNOR using minimum gates
Different levels of CIRCUIT
Special Characteristics of an IC
QUESTIONS
Q1 (Timing Diagram)
Q2 (Timing Diagram)
Q3 (Timing Diagram - DIfferent units)
Q4 (Timing Diagram)
Q5 (Output of Series of NOR gate )
Q6 (Output of combination of XOR )
Q7 (Circuit of NAND gates & diff delays)
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
TIMING CIRCUITS

 

 

Q-1 Show the level transitions in the input signal at the output line if Tp1 = 2ns, Tp2 = 2, Tp3=3ns, Tp4= 2 ns and assuming that all the transitions in input occur at t=0

Ans:  At node A: We have transition after the delay of Tp1 = 2 ns and at t=2 a HIGH to LOW pulse occurs

At node B:           We have 2 transitions at input: one LOW to HIGH at t=0 and other HIGH to LOW at t=2, hence we get output as a pulse of width 2 ns with 1st transition at t=2 and 2nd at t=4 ns as shown:

At node C:           We have a LOW to HIGH transition at t=5

 

OUTPUT:             Now we take OR of pulses at node B & C and we get the result as:

 

 

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