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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
BINARY LOGIC
LOGIC GATES
BOOLEAN ALGEBRA LAWS
CONSENSUS THEOREM
DIFFERENT FORS OF BOOLEAN EQUATIONS
RELATION B/W MAX & MIN TERMS
16 type of LOGIC FUNCTIONS
AND & OR GATE
Other GATES
XOR & XNOR gates
NEGATED & COMPLIMENTRY GATES
TRISTATE gates & DIP
Illustration of NEGATIVE & POSITIVE LOGIC
Relation B/W XOR & XNOR gates
UNIVERSAL GATES
Implementation of XOR using minimum gates
Implementation of XNOR using minimum gates
Different levels of CIRCUIT
Special Characteristics of an IC
QUESTIONS
Q1 (Timing Diagram)
Q2 (Timing Diagram)
Q3 (Timing Diagram - DIfferent units)
Q4 (Timing Diagram)
Q5 (Output of Series of NOR gate )
Q6 (Output of combination of XOR )
Q7 (Circuit of NAND gates & diff delays)
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
TIMING CIRCUITS

 

 

 

Q7- We implement the 3-input NAND gate circuit as follow and we are given the gate delay of d ns and

3 inputs are shown as:

And give us the output of the circuit and compare it with the ideal output.

Ans:  Firstly we NAND of A&B is calculated and then it is inverter to get A.B Then we NAND A.B and C to get NAND of A, B & C. The wave forms we get are as:

 

While the ideal output is

And now we compare the two outputs as:

We observe that following points are to be noticed while comparing:

  • There is a delay of 3d in the actual output
  • Also that actual output has shorter pulse width as compared to ideal.
  • As we have the pulse width as p – 3d, this pulse can even vanish if delay of the gate (d) is increased or pulse width (p) is decreased.

 

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