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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

CLOCK

A clock signal is defined by clock period or clock frequency. The clock period is defined as time interval after which clock repeats it self or we can define it as time gap between two consecutive falling edges or two consecutive rising edges and clock frequency is defined as number of clock pulses in a second.

Clock freq = 1/ clock period

Duty Cycle: of a periodic wave is defined as percentage of the clock period we have a HIGH pulse.

 i.e.         Duty cycle = (time for which pulse is 1)*100 / Clock period

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If width of HIGH pulse = width of LOW pulse = t as shown above.

Then Duty cycle = t/ 2t *100 = 50%

If we are given duty cycle = 33%, then it means

100/3 = (time for which pulse is 1)*100 / Clock period

Hence width of HIGH pulse = (1/3) * clock period as shown below:

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