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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

Clocking RS latch:

 We can control RS Latch with clock by ANDing both inputs with clock separately as:

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Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, inputs are not passed to the circuit and hence whole circuit is isolated from R & S. As this circuit is enabled only when Level of the CLK (OR E)  is HIGH and disabled when level of CLK (OR E)  is LOW, this is called LEVEL SENSITIVE (LATCH).  So when ever CLK (OR E) is high all the changes in the input are transmitted to the output as shown in the waveforms below:

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