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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

ASYNCHRONOUS INPUTS:

There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two types:

Active LOW: This means when the input is LOW, it would affect the output otherwise if input is HIGH then it causes no change.

Active HIGH: This means when input is HIGH then it can change the output otherwise if input is LOW, it doesn’t cause any change in the output.

These inputs can be adjusted in the circuit diagram of the flip-flop with Active HIGH DIRECT INPUTS as: www.exploreroots.com

Red colored line defines the boundary of the flip-flop.

The following table shows the output for various combinations of inputs with Active HIGH direct inputs:

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Similarly we can have the circuit for Active LOW direct inputs

 

Waveforms illustrating the functions of CLEAR & PRESET inputs for T Flip-flop are as:

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Note: When we have both PRESET & CLEAR equal to 1 (in Active high inputs) we have RACE CONDITION as PRESET tries to make output equal to 1 and CLEAR tries to make output equal to 0 simultaneously which is not possible..

Similarly we have RACE CONDITION when both PRESET & CLEAR are equal to 0 in Active low inputs.

 

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