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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

EDGE SENSITIVE LATCH (i.e. FLIP-FLOP):

Latches which are activated by the edge of the clock are called Flip-flops. If it is a positive edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the clock and if it is a negative edged flip-flop then inputs are accepted only when there is a HIGH to LOW transition in the clock signal.

When we use a pulse triggered latches in the circuit then every fluctuation in the input is visible in output. Hence we use edge triggered flip-flop and output is generated only depending upon the value of input at the clock edge. We represent the flip-flop similar to latch but in flip-flops we place a triangle near CLK terminal as shown: And to represent a negative edged flip-flop we place a circle before the triangle (as we do in case of inverter) shown below:

One way to make flip-flop respond to edge of the clock only, we use a RC circuit to produce a edged clock rather than a pulsed clock. This RC circuit generates spikes in response to the transitions in the clock pulse as shown below and we use either positive or negative spikes and neglecting the other spike.

We can get only positive spike using following circuit:

We can also achieve edge triggering by other methods as explained next.

 

 

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