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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
DERIVATION-PART I
DERIVATION-PART II
DERIVATION-PART III
DERIVATION-PART IV
DERIVATION-PART V
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

DERIVING THE CIRCUIT OF FLIPFLOP (from digital components):

 To understand the logic let’s consider a basic circuit of an inverter with a feedback as below:

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Now what would be the output of the circuit?

 We know what ever is at input, we’ll get inverse of that at output and as output is fed back to input so again it would be inverted and this way we’ll have a pulse oscillating between 0 and 1. Hence the output is as follow:

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And width of the pulse (either LOW or HIGH) would be equal to the total delay of the gate and wires. Hence we have the clock period equal to 2*(gate delay + wire delay).

 

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