Digital Electronics NUMBER SYSTEM BINARY CODES BOOLEAN ALGEBRA K MAPS COMBINATIONAL CKT SEQUENTIAL CIRCUITS INTRODUCTION CLOCK BISTABLE MULTIVIBRATOR DERIVATION of FLIPFLOP circuit DERIVATION-PART I DERIVATION-PART II DERIVATION-PART III DERIVATION-PART IV DERIVATION-PART V RS FLIPFLOP RS FLIPFLOP(NAND IMPLEMENTATION) R'S' FLIPFLOP Clocking RS LATCH Other LATCHes Timing problem in LATCHES ASYNCHRONUS INPUTS Parameters of CLOCK pulse QUESTIONS(LATCH using MUX) EDGE SENSITIVE LATCH (i.e. FLIPFLOP) MASTER SLAVE FF D FF USING MUX TIMING PARAMETERS OF FF CHARACTERISTIC EQUATIONS OF FFs EXCITATION TABLES OF FF CONVERSION OF 1 FF TO OTHER FF as 1bit MEMORY CELL REGISTERS SHIFT REGISTERS RING COUNTER JOHNSON COUNTER QUESTION(Serial Data transfer) ASYNCHRONOUS COUNTERS RIPPLE COUNTER COUNTER other than MOD-2n Designing COUNTER Using K-MAPS QUESTION(MOD 6 counter) QUESTION(Counter design) DOWN COUNTER QUESTION(Counter design) GLITCH SYNCHRONOUS COUNTER COMPARISON B/W SYNC. & ASYNC. COUNTERS CLOCK SKEW QUESTION(Maximum frequency question) QUESTION(Maximum frequency question) MORE QUESTIONS TIMING CIRCUITS

DERIVING THE CIRCUIT OF FLIPFLOP (from digital components):

To understand the logic let’s consider a basic circuit of an inverter with a feedback as below:

Now what would be the output of the circuit?

We know what ever is at input, we’ll get inverse of that at output and as output is fed back to input so again it would be inverted and this way we’ll have a pulse oscillating between 0 and 1. Hence the output is as follow:

And width of the pulse (either LOW or HIGH) would be equal to the total delay of the gate and wires. Hence we have the clock period equal to 2*(gate delay + wire delay).