Digital Electronics NUMBER SYSTEM BINARY CODES BOOLEAN ALGEBRA K MAPS COMBINATIONAL CKT SEQUENTIAL CIRCUITS INTRODUCTION CLOCK BISTABLE MULTIVIBRATOR DERIVATION of FLIPFLOP circuit RS FLIPFLOP RS FLIPFLOP(NAND IMPLEMENTATION) R'S' FLIPFLOP Clocking RS LATCH Other LATCHes Timing problem in LATCHES ASYNCHRONUS INPUTS Parameters of CLOCK pulse QUESTIONS(LATCH using MUX) EDGE SENSITIVE LATCH (i.e. FLIPFLOP) MASTER SLAVE FF D FF USING MUX TIMING PARAMETERS OF FF CHARACTERISTIC EQUATIONS OF FFs EXCITATION TABLES OF FF CONVERSION OF 1 FF TO OTHER FF as 1bit MEMORY CELL REGISTERS SHIFT REGISTERS RING COUNTER JOHNSON COUNTER ASYNCHRONOUS COUNTERS RIPPLE COUNTER COUNTER other than MOD-2n Designing COUNTER Using K-MAPS QUESTION(MOD 6 counter) QUESTION(Counter design) DOWN COUNTER QUESTION(Counter design) GLITCH SYNCHRONOUS COUNTER COMPARISON B/W SYNC. & ASYNC. COUNTERS CLOCK SKEW QUESTION(Maximum frequency question) QUESTION(Maximum frequency question) MORE QUESTIONS TIMING CIRCUITS

Q- Design a circuit to transfer data serially from one shift register to other.

Ans:  If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not be as required. Hence we have to give a control pulse which would control that only N clock cycles are given to the registers. The circuit diagram is as follow:

If we are to transfer data between 4 bit register then control pulse would be 4 clock cycles wide as shown so that only 4 clock cycles are passed.

Following table would show the values of two registers at different clock cycles

Register 1                            Register 2            Output

1101                                       1001

First clock                            1110                                       1100                       1

2nd clock                               0111                                       0110                       0

3rd clock                                1011                                       1011                       0

4th                                           1101                                       1101                       1

Hence we see that register1 retains its contents and register2 gets the value of register2 which was required.