Digital Electronics NUMBER SYSTEM BINARY CODES BOOLEAN ALGEBRA K MAPS COMBINATIONAL CKT SEQUENTIAL CIRCUITS INTRODUCTION CLOCK BISTABLE MULTIVIBRATOR DERIVATION of FLIPFLOP circuit RS FLIPFLOP RS FLIPFLOP(NAND IMPLEMENTATION) R'S' FLIPFLOP Clocking RS LATCH Other LATCHes Timing problem in LATCHES ASYNCHRONUS INPUTS Parameters of CLOCK pulse QUESTIONS(LATCH using MUX) EDGE SENSITIVE LATCH (i.e. FLIPFLOP) MASTER SLAVE FF D FF USING MUX TIMING PARAMETERS OF FF CHARACTERISTIC EQUATIONS OF FFs EXCITATION TABLES OF FF CONVERSION OF 1 FF TO OTHER FF as 1bit MEMORY CELL REGISTERS SHIFT REGISTERS RING COUNTER JOHNSON COUNTER QUESTION(Serial Data transfer) ASYNCHRONOUS COUNTERS RIPPLE COUNTER COUNTER other than MOD-2n Designing COUNTER Using K-MAPS QUESTION(MOD 6 counter) QUESTION(Counter design) DOWN COUNTER QUESTION(Counter design) GLITCH SYNCHRONOUS COUNTER COMPARISON B/W SYNC. & ASYNC. COUNTERS CLOCK SKEW QUESTION(Maximum frequency question) QUESTION(Maximum frequency question) MORE QUESTIONS TIMING CIRCUITS

ASYNCHRONOUS COUNTERS - MOD-2 counter:

If we see that flip-flop is a mod-2 counter with starting count as 0. If we connect J & K to HIGH and supply clock to the flip-flop, we’ll see that flip-flop would count pulses 0, then 1 and as it is a MOD-2 counter so it’ll reset and again count from 0.

And the output is as:

Also note that output pulse is of half the original frequency of the clock. Hence we can say that flip-flop acts as a Divide by 2 circuit.