Digital Electronics NUMBER SYSTEM BINARY CODES BOOLEAN ALGEBRA K MAPS COMBINATIONAL CKT SEQUENTIAL CIRCUITS INTRODUCTION CLOCK BISTABLE MULTIVIBRATOR DERIVATION of FLIPFLOP circuit RS FLIPFLOP RS FLIPFLOP(NAND IMPLEMENTATION) R'S' FLIPFLOP Clocking RS LATCH Other LATCHes Timing problem in LATCHES ASYNCHRONUS INPUTS Parameters of CLOCK pulse QUESTIONS(LATCH using MUX) EDGE SENSITIVE LATCH (i.e. FLIPFLOP) MASTER SLAVE FF D FF USING MUX TIMING PARAMETERS OF FF CHARACTERISTIC EQUATIONS OF FFs EXCITATION TABLES OF FF CONVERSION OF 1 FF TO OTHER FF as 1bit MEMORY CELL REGISTERS SHIFT REGISTERS RING COUNTER JOHNSON COUNTER QUESTION(Serial Data transfer) ASYNCHRONOUS COUNTERS RIPPLE COUNTER COUNTER other than MOD-2n Designing COUNTER Using K-MAPS QUESTION(MOD 6 counter) QUESTION(Counter design) DOWN COUNTER QUESTION(Counter design) GLITCH SYNCHRONOUS COUNTER COMPARISON B/W SYNC. & ASYNC. COUNTERS CLOCK SKEW QUESTION(Maximum frequency question) QUESTION(Maximum frequency question) MORE QUESTIONS TIMING CIRCUITS

DOWN COUNTER: (Reverse counting)

Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next flip-flop.

And the output waveform would be as:

Or

And the output waveform would be as:

In both cases we take (Q4 Q3 Q2 Q1) 2 as value of the count

Or

We can just use the same circuit as the UP counter but

Consider the following circuit

And we see that this circuit is a UP counter which count from 0 to 7 and then it is reset but the same circuit can also work as DOWN counter when we take count as combination of inverted outputs for each FF. i.e.. Hence output count of the above circuit would go from 7 to 0 and then again it is set to 7.