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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

GLITCH:

A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop.  e.g.

  • We can see in the wave-forms given above for MOD-14 counter that there is a glitch in the Q2 signal which is produced due to delay of AND gate to reset the FF.
  • Also a glitch can be generated when we AND two signals and there is a slight delay between two signals. Such a combinational circuit is used when we have to transfer data serially between two registers discussed already and we need limited number of clock cycles for proper working.

The following circuit was designed to produce enable signal (with 4 clock cycles)

But due to slight delay in the one of the input signals there is glitch in the output which would lead to mal-functioning of the circuit.

 

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