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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

Synchronous Counter

In synchronous counters we have the same clock signal to all the flip-flops.

MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s

 

We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & K for 1st FF as 1 and hence output of 1st FF toggles and changes from 0 to 1. But when 1st cock edge had come output of 1st FF was 0. Hence J & K for 2nd FF for 1st edge are 0. So output of this FF doesn’t change and we get Q1=0. so the output is (Q1Q0)2= 012.

On the next edge, output of 1st FF changes from 1 to 0 as J & K are always 1 for this FF. Inputs for 2nd edge for 2nd FF are J=1 & K=1. Hence output changes from 0 to 1. so we get the count as (Q1Q0)2= 102.

Similarly on the next edge we’ll get the output count as (Q1Q0)2= 112.

And on the 4th clock edge both the outputs get reset and we get the output as (Q1Q0)2= 002 and again whole procedure is repeated.

We’ll be studying other synchronous counter when we discuss the design of synchronous circuits later.

 

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