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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

QUESTION

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns     T (hold time) = 4ns             T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in the above circuit.

Ans: We firstly represent the delays wrt edge of 1st FF as

 

And the delayed input must reach before the edge reaches 2nd flip-flop

The clock skew is basically the delay in clock signal reaching 2nd flip-flop. Hence this is quiet similar to the previous question of a buffer in the pathway of clock.

Hence Clock time period is T = T CLK to Q + cdelay + Setup time – Clock Skew

= 9 + 13 + 5 – 3 = 24 ns

And maximum frequency of the circuit is F max = 1 / 24 = 4.16 MHz  

 

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