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Digital Electronics
NUMBER SYSTEM
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CLOCK
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Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

QUESTIONS

Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns  T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. Also there is problem of clock skew in the system. We also have to identify the pair of registers between which we need to know the value of clock skew.

Assume value of clock skew between required pair of registers.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges. It’s only the clock skew which is going to affect the value of maximum frequency. We represent everything as:

 

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

FF1         Tmin = setup FF1 = 5 ns                                

FF2         Tmin = T1 CLK to Q + cdelay1 + setup FF2 – clock skew (b/w FF1 & FF2)

= 9 + 13 + 4 – clock skew (b/w FF1 & FF2) = 26 – 3 = 23 ns

FF3         Tmin = T2 CLK to Q + cdelay2 + setup FF3 – clock skew (b/w FF3 & FF2) = 7 + 16 + 4 – 3 = 24 ns

Note: We can easily notice that we need the value of clock skew between only adjacent pair of Flip-flops.  We have assumed the value of skew as 3 ns between the pairs.

And the minimum time period to satisfy every condition at every clock edge is 24 ns

Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz

IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while it’s meaningless to know about the cock skew between other pair of flip-flops. Hence in the above case we only need to know the value of clock skew between FF1 & FF2 and FF2 & FF3 while skew between FF1 & FF3 is meaningless.

  

 

 

 

 

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