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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP circuit
RS FLIPFLOP
RS FLIPFLOP(NAND IMPLEMENTATION)
R'S' FLIPFLOP
Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
MORE QUESTIONS
TIMING CIRCUITS

 

RS FLIPFLOP

When R=0, S=0 we don’t have a change in the output in the circuit.

When R=0, S=1 we have output as Q=1 and Q bar = 0

When R=1, S=0 we have the output as Q=0 and Q bar = 1

But when we have R=1, S=1, both R and S make outputs of their NOR gates 0. Hence we have Q=0,         Q bar = 0 which is not a valid case as Q & Q bar should be compliment of each other and hence we don’t consider this case. This is called RACE CONDITION. All these cases can be collectively represented in a table as follow:

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Let’s draw the timing diagram of the RS latch: t is the delay for a NOR gate.

 

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Initially we have R=0, S=0 and Q=0. When value of S changes to 1, we see in the circuit of RS latch, output of NOR gate (which is Q’) becomes 0 after delay of t ns. Hence both Q & Q’ are 0.Now inputs of other NOR gate become R=0 & Q’=0 and hence we get Q as 1 after another delay of t ns which is shown in the timing diagram. Similarly other outputs are shown.

 

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