It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times.
e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.
CAUSES: There are basically 2 reasons due to which clock skew exists in the system:
- Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance.
- Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.
Effects of clock skew:
- Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations.
- Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).