A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells. Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse. But […]
Tag: flip flop
Flip flop = 1 bit Memory
1-bit Memory Cell: We know that flip-flop can store either zero or one permanently until a change is made in the inputs. Hence flip-flop would work as 1-bit memory cell.
Conversion: Generic
CONVERSION OF ONE FLIP-FLOP TO OTHER: As we have already seen from the way we derived D flip-flop from RS flip-flop or the way we derived T flip-flop from JK flip-flop or the way we derived JK flip-flop from RS flip-flop by feeding back outputs that to derive a flip-flop from the other flip-flop we need to design a combinational arrangement […]
Conversion: D to T & T to D FF
Similar to previous conversions, we get the circuits as follow: D FF to T FF: T FF to D FF: Note: We have not shown the clock but we can attach the clock signal to the given FF. Similarly we can obtain other conversions.
Conversion: RS to D flip-flop
Let’s first now derive the D flip-flop from RS flip-flop which we have already done: We first write the truth table for required D flip-flop as Now we write the excitation table of given FF SR flip-flop as Now we need to make a arrangement so that we manipulate input D to inputs R, S […]
Excitation table of Flip flops
Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change. E.g. As in truth table we say for T […]
Characteristics Equation of Flip flops
RS Flip flops: The truth table for RS Flip-flop is as follow: Now let’s draw the K-map and get the equation for output Q. As the Qp and Qp bar are compliment of each other so we’ll consider only one of those in K-MAP D FLIP-FLOP: Truth table is as: The equation we get is JK FLIP-FLOP: The truth […]
Q4: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]
Q2: Maximum frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns Ans: As input to first flip-flop is directly available and […]
Timing parameters of a flip flop
There are basically 3 types of factors which affect the working of a flip flop: 1. Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If […]