Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in […]
Tag: timing diagram
Down Counter (Reverse counting)
Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next […]
Counter other than MOD-2n
Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example: Design […]
Q: Serial Data Transfer
Q- Design a circuit to transfer data serially from one shift register to other. Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not […]
Q1: Timing Diagram
Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as: T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as: Find Maximum frequency. Ans: I’ll recommend drawing the 1st edge of clock and then to […]
Timing parameters of a flip flop
There are basically 3 types of factors which affect the working of a flip flop: 1. Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If […]
Problem in Master Slave
We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs And we see that at the 4th and 5th edge we have the wrong transitions. Why so? Before […]
Master slave Flip flop
We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level. Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]
Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two […]
Timing Problem in Latches
Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown: Suppose we have the following circuit: In this circuit when […]