Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder. Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is […]
Tag: clear
Q: Design custom ripple counter
Q- Design the ripple counter whose output sequence is represented by the following state diagram. Ans: As we can see that it is a down counter so we’ll be using Q bar of all flip-flops as clock to next flip-flops (negative edged FFs). We draw the table as Q2 Q1 Q0 OUTPUT 0 0 0 0 […]
Johnson Counter
While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we connect Q bar of last to D of 1st FF as shown below and we also don’t need to connect preset of 1st FF. This is also called Twisted Ring counter: And JK implementation is as follow: And we have […]
Parameters of clock pulses
Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some minimum values for proper operation of every flip-flop. This width is measured between 50% transition points of rising and trailing edges of the given signal. Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the […]
Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two […]