Categories

## SCHMITT Trigger

As we have generally slow changing DATA signals i.e. DATA signals have slow rising and falling edges. And use of these signals creates problems in the working of Digital circuits. Hence to avoid these problems we use SCHMITT TRIGGER to sharpen up the edges of DATA. The transfer characteristics of this trigger are as follow:

We have only 2 output voltage levels Vo- & Vo+ and there are 2 input voltage thresholds V1 & V2. the SCHMITT TRIGGER follows the above characteristics i.e. when ever input voltage is increased from 0, we have the output voltage as Vo- and output remains the same till input voltage is less than V2. Hence when ever there is an increase in the input voltage, transition would occur only when input voltage becomes greater than V2.

When-ever input voltage is decreased from the high value (>V2), we have the output as Vo+ and the output remains the same until input voltage becomes less than V1.

Hence behavior of SCHMITT TRIGGER depends on whether input is increasing or decreasing and trigger is said to give hysteresis of V2 – V1. This is used to eliminate the effect of noise on the signal. We illustrate this fact using the following example.

Suppose we have the following signal with superimposed noise and we take two cases: with small hysteresis V2 – V1and with large hysteresis V2 – V1—and notice the effect of SCHMITT TRIGGER

Small hysteresis V2 – V1+As voltage is less than V1+, hence initial output is Vo-. When the voltage increases to greater than V2, output jumps suddenly from Vo- to Vo+. Now output voltage remains same till input voltage drops below V1+. When voltage drops below V1+, we get the output as Vo-. After some time input voltage again increases beyond Vand hence output again jumps to Vo+.

Large hysteresis V2 – V1–: As voltage is less than V1- , hence initial output is Vo-. When the voltage increases to greater than V2, output jumps suddenly from Vo- to Vo+. Now output voltage remains same till input voltage drops below V1+. When voltage drops below V1+, we get the output as Vo-.

We represent the outputs of SCHMITT TRIGGER below:

And we can see that we get a clean square wave for large hysteresis while for small hysteresis we get many transitions in the output but it is still better than the output without using SCHMITT TRIGGER.

Categories

## 555 Timer: Astable Operation

In Astable operation, we have no stable states. Hence we say that timer doesn’t stay in any of the two states indefinitely i.e. vibrates between the two states. Hence we don’t need trigger in this case. This is also called Astable Multi-vibrator. This is also called free-running multi-vibrator. When-ever we give power to the timer, we get the rectangular oscillating output signal.

The following diagram would explain the working of the Astable Multi-vibrator:

Working of this circuit is similar to Monostable multi-vibrator. In this circuit voltage of the capacitance oscillates between Vcc/3 and 2 Vcc/3.

Suppose initially we have Q=0 & Q’=1. As Q is 0, transistor is turned OFF and hence capacitor starts charging through R1 + R2. When the voltage of capacitor goes greater than 2 Vcc/3, output of upper Op-amp gets 1 and hence S=1 & R=0 and due to this Q becomes HIGH and Q’ goes LOW.

Now as we have Q=1 & Q’=0. As Q is 1, transistor is turned ON and hence capacitor starts discharging through R2. When the voltage of capacitor becomes less than Vcc/3, output of lower Op-amp gets 1 and hence S=0 & R=1 and due to this Q becomes LOW and Q’ goes HIGH.

Now again we have Q=0 & Q’=1 and whole procedure is repeated. Hence we get the oscillating output as illustrated follow:

In the figure above W is equal to the time in which capacitor is charged to 2 Vcc/3 from Vcc/3 and P is equal to the time in which capacitor is discharged from 2Vcc/3 to Vcc/3. Hence

W= 0.693 (R1+R2) C

P= 0.693 R2 C

So the time period of output is T= 0.693 (R1+2 R2) C

We can vary the duty cycle of output pulse by changing the value of R1 & R2 and duty cycle is defined as

D= W/T = 0.693 (R1+R2) / 0.693 (R1+2 R2) C = (R1+R2)/ (R1+2 R2)

And frequency of the timer is F= 1/T = 1.44/ (R1+2 R2) C

Categories

## 555 Timer: Monostable operation

In monostable operation we have only one state stable and other state unstable. We have a input named Trigger to the 555 Timer. When we give no trigger timer stays in the stable state but when we give trigger then timer goes to the other state for a fixed time period and then goes back to the stable state. The stable state for 555 Timer is LOW state while HIGH state is unstable state. Hence 555 Timer has a LOW output voltage initially. When we given trigger then timer output voltage goes from LOW to HIGH and stays HIGH for W time delay and then resets again.

A Multi-vibrator is 2-state circuit which has either a zero or one or two stable states. And as in monostable operation of 555 timer we have one stable state, hence we also call this timer as Monostable Multi-vibrator. Functional diagram of monostable multi-vibrator is given on next page. In the diagram, as we have three 5 Kohm resistors in series hence the circuit is called 555 Timer (Triple 5 timer). Due to this arrangement we have 2Vcc/3 voltage at node A and Vcc/3 voltage at node B.

Initially we have output equal to zero i.e. Q’= 0 & Q=1. As Q=1, transistor gets ON and hence capacitor is discharged and hence S becomes ZERO and R is also ZERO as initial value of Trigger is Vcc.

Hence in stable state

S=0         R=0        output=0             and        capacitor C is discharged

When we give a trigger at the input (i.e. a LOW voltage pulse is given for small time), lower op-amp gives 1 as voltage at –ve terminal becomes less than Vcc/3. Hence R becomes 1 and Q becomes 0 and Q’=1 and output goes HIGH. Now as Q=0, this cuts-off the transistor and hence capacitor is allowed to charge through resistance R. When capacitor voltage becomes greater than 2Vcc/3, output of upper op-amp becomes   1 and hence S=1, R=0 which makes Q=1 and Q’=0. And output is again reset. Hence a trigger at the input makes output as 1 for some time W i.e. a rectangular pulse of width W is obtained.

The value of W is slightly more than the time in which capacitor is charged from 0 to 2Vcc/3. We know that in one time constant RC, capacitor is charged to 63.2% but we need to charge capacitor to 2Vcc/3 = 66.6%. if we solve the equations then we’ll get

W= 1.1 RC

The following waveforms represent the working of monostable:

Categories

## Timing Circuits: Introduction

The timing circuits are the special purpose circuits which are generally used in digital circuits. We have the following important types of timing circuits:

1. 555 Timers are used in timing circuits very often as they are more reliable and lost cost. We have the two modes of operation of 555 Timer:

• Monostable operation
• Astable operation

2. Schmitt Trigger: This is used to sharpen up falling and rising edges of DATA signal.

Categories

## Q8: MOD 8 Counter

Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder.

Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock.  Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is ignored and 000 is fed into register. We have the circuit as:

In the circuit block of 3 FFs is a register with 2 common inputs.

Categories

## Q7: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns,   T (AND) = 4 ns, T (OR) = 4 ns,     T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time –clock delay for 2nd FF = 2 + 6 + 5–2 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz

(b) HOLD TIME:

At 1st FF K input & one input of AND gate for J input is given externally which is supposed to be held stable for hold time but the other input is a feedback from 2nd FF and this input changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1st FF. hence hold time condition is satisfied for 1st FF.

At 2nd FF K inputchanges after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17 ns i.e. more than Hold time

one J input (o/p of 1st FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 = 19 ns i.e. more than Hold time

While other input to J through OR gate is a feed back from o/p of 2nd FF and changes only after time       T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time (=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is equal to hold time. Hence condition satisfied.

Hence we can also note that HOLD time doesn’t depend upon the clock frequency while SETUP time violation depends upon the clock frequency.

Categories

## Q6: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns             T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3 ns & 2 ns respectively.

Ans: The combinational circuit after the 2nd FF doesn’t affect the clock frequency of the circuit as there is no gated component after that circuit. Hence we represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that

Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF

= 9 + 13 + 5 – 2 = 25 ns

And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz

Categories

## Q5: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns  T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges it’s only the delay which has been introduced in the path way of clock signal. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

FF1         Tmin = setup FF1 = 5 ns

FF2         Tmin = T1 CLK to Q + cdelay1 + setup FF2 – clock delay= 9 + 13 + 4 – 2 = 24 ns

FF3         Tmin = T2 CLK to Q + cdelay2 + setup FF3 – clock delay= 7 + 16 + 4 – 2 = 25 ns

As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is subtracted which can also be seen from the diagram.

Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.

And the minimum time period to satisfy every condition at every clock edge is 25 ns

Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz

Categories

## Q4: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and delay of other components is T (buf) = 2ns,ï¿½ ï¿½  T (AND) = 4 ns, T (OR) = 4 ns,ï¿½ ï¿½ ï¿½ ï¿½  T (NOT) = 2 ns in the following circuit.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time â€“clock delay for 2nd FF = 9 + 6 + 5â€“2 = 18ns Maximum Clock frequency = F max = 1/18 = 5.55 MHz

Categories

## Q3: Binary Multiplier

Q-Implement binary multiplication using shifter:

Eg. If we are multiply 11 * 4

Then 11 = 1011                  4 = 0100

Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD & Shift or if bit of multiplier is 1 then ADD multiplicand and SHIFT and if bit of multiplier is 0 then ADD zero (or don’t perform ADD but just) SHIFT. We store multiplier in register Q & multiplicand in A and use adder as:

Now I’ll show the contents of shifter at every clock tick if we have to find A* B =  1011 * 0100

Clock tick                             contents of register                                        Function

1st tick                                   0              0000       0100                       Initial data is stored in register from inputs

2nd tick                                  0              0000       0100                       Result of adder is stored

2nd tick                                  0              0000       0010                       it is shifted towards right

3rd tick                                   0              0000       0010                       Result of adder is stored

3rd tick                                   0              0000       0001                       shifted right again

4th tick                                   0              1011       0001                       firstly result of adder is stored

4th tick                                   0              0101       1000                       now right shifted

5th tick                                   0              0101       1000                       Result of adder is stored

5th tick                                   0              0010       1100                       Again right shifted

And we get the answer as 001011002