Categories

## Question 7: ANALYSIS OF NAND CIRCUIT

Q7- We implement the 3-input NAND gate circuit as follow and we are given the gate delay of d ns and

3 inputs are shown as:

And give us the output of the circuit and compare it with the ideal output.

Ans:  Firstly we NAND of A&B is calculated and then it is inverter to get A.B Then we NAND A.B and C to get NAND of A, B & C. The wave forms we get are as:

While the ideal output is

And now we compare the two outputs as:

We observe that following points are to be noticed while comparing:

• There is a delay of 3d in the actual output
• Also that actual output has shorter pulse width as compared to ideal.
• As we have the pulse width as p – 3d, this pulse can even vanish if delay of the gate (d) is increased or pulse width (p) is decreased.
Categories

## Question 6: OUTPUT OF XOR CIRCUITS

Q6- What is the output of the circuits given below?

Ans:   Here we see that if we have X= 0 then outputs of both circuits is zero.

1. But when we have X=1, then output of the circuit with even number of XOR gates is 1
2. And when we have X=1 and number of XOR gates is Odd then we get the output as 0
Categories

## Question 5: OUTPUT OF CIRCUIT

Q5- What is the output of the following circuit? Ans:  This circuit may look simple to you as one has to just evaluate every NOR gate and get the final output but I say it is even simpler than this. Let’s analyze the truth table of NOR gate:

And we see that even if only one of the 2 inputs is 1 then we need not find out the other input and we can get the output.

As in the above circuit we have one input as 1 to the last NOR gate so we can say that output of the above circuit is ‘0’ without calculating the outputs of other NOR gates.

Categories

## Question 4: TIMING DIAGRAM

Q4- Draw the output waveform of the NAND gate when we have the two inputs as follow and delay of the gate is equal to 12.5 ns when output goes from LOW to HIGH and delay is 17.5 ns when output goes from HIGH to LOW.

Ans: To get the exact output waveform we firstly draw the output waveform without considering any delay and hence we get the output waveform as:

Now to get the actual output we’ll delay the output HIGH to LOW edge by 17.5 ns and LOW to HIGH edge by 12.5 ns.

Or

We can directly check the output of the gate and delay the output accordingly if out is HIGH to LOW or LOW to HIGH and hence no need to draw a waveform without considering the delay. Categories

## Question 3: TIMING DIAGRAM (Diff Units)

Q3- Sometimes delay of gates and the waveforms are given in different units. So let’s take such example with same circuit and delay as above but waveforms as below:

Ans: So we convert the delay into ps (Pico seconds)

So delay for NOR= 3ns = 3000ps

Delay for BUFFER =1ns=1000ps

Delay for AND=4ns=4000ps

So the waveforms of Output are as follow: Categories

## Question 2: TIMING DIAGRAM

Q2- Draw the output of the circuit when waveforms of inputs X & Y are as given.

Take initial output values as zero. We’ll first calculate output of NOR gate and delay the output by 3ns. Then we draw output of BUFFER with delay of 1ns and finally we take AND of 2 outputs and induce delay of 4 ns as shown below:

We have marked change of level with time for clarity. Categories

## Question 1: TIMING DIAGRAM

Q-1 Show the level transitions in the input signal at the output line if Tp1 = 2ns, Tp2 = 2, Tp3=3ns, Tp4= 2 ns and assuming that all the transitions in input occur at t=0

Ans:  At node A: We have transition after the delay of Tp1 = 2 ns and at t=2 a HIGH to LOW pulse occurs

At node B:           We have 2 transitions at input: one LOW to HIGH at t=0 and other HIGH to LOW at t=2, hence we get output as a pulse of width 2 ns with 1st transition at t=2 and 2nd at t=4 ns as shown:

At node C:           We have a LOW to HIGH transition at t=5

OUTPUT:             Now we take OR of pulses at node B & C and we get the result as:

Categories

## Special Characteristics of an IC

A gate IC can be realized using different logic families (explained later) and hence every gate have the following characteristics which may vary with different logic family. The most important parameters are the following

Fan-out: It specifies the maximum number of standard gates that output of a gate can rive without affecting its own working. This normally depends upon the amount of current needed by a gate of same IC family. We generally connect output of a given gate to the inputs of other gates but there is a limit on the number of gates to which the output of a given gate can be inputted and this limit is called fan out of the given gate. If we exceed this limit then this may cause the malfunctioning of the circuit because the given gate may not be able to provide enough power to the gates which are connected to the output of the given gate.

When we have logical 0 at the output current is drawn into the circuit while when we have output as logical 1 then current is supplied to the load. So number of loads that can be connected to the output varies whether we have output as logical 1 or output as logical 0 but we take worst of the two as fan-out e.g. A gate in the TTL family can take load of 10 gates at logical 1 while 5 gates at logical 0. So we take fan-out as 5.

If we have fan out of he given gate as N, then we can connect the output of the given gate to N different gates of same family as shown below.

If we have fan out of he given gate as N, then we can connect the output of the given gate to N different gates of same family as shown below.

Some gates like XOR, BUFFER, INVERTER consume loading factor of 2 i.e. their load is equivalent to 2 usual gates.

If we consider this then a gate with loading factor of 5 can drive 2 XOR gate inputs and 1 OR or AND gate input.

BUFFER has fan-out of 25

Fan-in: It is basically the number to which we can extend the inputs of a gate. Generally this is equal to 8. This means that we can have a gate with maximum of 8 inputs as shown below

Power dissipation:  It is the average of powers dissipated in a gate with all inputs at logic 1 and the gate with all inputs at logic 0 and expressed in mW. If we have a IC with 4 gates then we need power supply which is equal to 4 times the power dissipation of the gate. It is an important factor. Industry is working continuously to decrease this factor further and further.

Propagation delay:  It is the average transition time for a signal to propagate from input to output. If we make a change in the binary signal at the input at time t=0 and we observe the corresponding change in the output at time t sec. Then the propagation delay for gate is taken as t. it is generally expressed in ns. The gate must have the minimum propagation delay. Propagation delay depends on the number of levels we have in a circuit. If we have 3 levels of gates in a circuit and each gate provides a delay of t ns then we have the total delay of the circuit as 3t ns.

Noise margin:  It is maximum noise which can be tolerated at the input of the circuit i.e. the maximum amount of noise which when added to the input does not give an undesirable change in the output. The noise if generally of two types: DC noise-that leads to the shift in the voltage level of the signal and the AC noise which is a random signal that can be created by any other switching signal and this signal s superimposed over the input signal. Noise margin should be as high as possible.

Categories

## Division of the circuit in different levels

We have some eternal inputs which are used directly or indirectly by the elements of the circuit to obtain output. The elements or the gates which receive all their input from the external inputs directly constitute the logical level one of the circuit while the gates which receive at least one input from the output of the gates of level one and not higher are under the logical level two of the circuit. Similarly we get 3rd and 4th level and so on.

From the above circuit we can see that only gate 1 is receiving all the input from external inputs derectly hence gate 1 is in logic level1

As gate 2 is receiving one input directly while the other input from gate 1 so gate 2 is in level 2 of the circuit.

Gate 3 receives the1st input directly from external input, 2nd input from output of gate 1 but it is not a level 2 gate as it is also receiving its third input which is from gate 2 (a level 2 gate), hence gate 3 is a level 3 gate.

Categories

## Question: Implement XNOR gate using NOR only

Q- Implement 2 variable XNOR gate using NOR only in minimum number of gates.

F= x XNOR y = (x XOR y)’

F’= (x XOR y) = x’y+xy’ = x’y+xy’+xx’+yy’ = (x+y) (x’+y’)

F’= x’(x+y) + y’(x+y)

Take compliment

F= (x’(x+y) + y’(x+y))’ = (x’(x+y) )’ . (y’(x+y))’ =(x+(x+y)’). (y + (x+y)’)

Take compliment again

F’= ( (x+(x+y)’). (y + (x+y)’) )’ = (x+(x+y)’)’ + (y + (x+y)’)’

Take compliment again

F= [ (x+(x+y)’)’ + (y + (x+y)’)’ ]’

Now we can implement the circuit of XNOR gate using NOR gates Hence we need only 4 NOR GATES to implement XNOR gate and we require 5 NOR gates to implement XOR gate with 5th NOR gate used as inverter and placed in front of 4th NOR gate.