Q- Implement a basic ALU which performs the operations of logical AND, logical OR, ADD, SUBRACT depending on the values of S1 & S0
Ans: We need to use an ADDER, AND gate, OR gate and some MUXes to implement the above function. We select the functions using the two variables S0 & S1 as:
S1 S0 F (S0, S1)
0 0 AND
0 1 OR
1 0 ADD A & B
1 1 SUBTRACT B FROM A
Firstly we’ll select one out of two logical operations and one out of two arithmetic operations using 2 to 1 MUX and then we select one out of 2 already selected operations and get the result.
Q- Can we implement 4 to 1 MUX using (a) three 2 to 1 MUX (b) only two 2 to 1 MUX and a OR gate & NOT gate?
Ans: (a) We can implement 4 to 1 MUX from 2 to 1 MUX as shown below:
(b) We have already implemented 8 to 1 MUX using two 4 to 1 MUX and one 2 to 1 MUX but as here we have to implement without using 2 to 1 MUX but a OR gate hence we’ll utilize Enable pin of the MUX and skip the use of 2 to 1 MUX as shown below:
Q- Design and implement the following with a combinational circuit (with A and B being 4-bit numbers):
S2 S1 S0 Output
0 0 0 2A
0 0 1 A plus B
0 1 0 A plus B’
0 1 1 A minus 1
1 0 0 2A + 1
1 0 1 A plus B plus 1
1 1 0 A minus B (2’s compliment)
1 1 1 A
Ans: We need one 4-bit parallel ADDER and MUX to implement the above. As we can see that we need at least one A at the input of ADDER so put A at one of the inputs
And for the 2nd input we have to choose out of different options, hence we use a MUX
And we see that we have to add an extra 1 when s2=1
When S1=0 S0=0 we need 2nd input as A to get 2A & 2A+1, when S1=0 S0=1 we need 2nd input as B to get A + B & A+B+1, when S1=1 S0=0 we need 3rd input as B’ to get A + B & A+B’+1 as B’+1 is 2’s compliment of B hence A+B’+1 = A – B, when S1=1 S0=1 we need 4th input as – 1(11112) to get A – 1 & A – 1 + 1 = A
Q- Design and implement the following with a combinational circuit (with A and B being 4-bit numbers):
S1 S0 Output
0 0 A plus B
0 1 left shift A
1 0 A plus B plus 1
1 1 2A + 1
Ans: We need one 4-bit parallel ADDER and MUX to implement the above. As we can see that we need atleast one A at the input of ADDER so put A at one of the inputs
And for the 2nd input we have to choose out of different options, hence we use a MUX
And we see that we have to add an extra 1 when s1=1 & s0=0 and s1=1 & s0=1. In both cases we have s1=1 so we attach s1 to carry pin also.
Left shifting A would make it 2A hence we add A to A to get left shift of A.
Q- Draw the circuit to check a PALINDROME number of even bits.
Ans: Palindrome number (in bits) is the number which is same whether seen from the first and the last bit. E.g. 1001, 0110, 0000, 1111 in 4 bits
So to check this we need to have same value of bit at 1st bit and 4th bit, 2nd and 3rd bit position for a 4-bit number. For a 6-bit number we need to have same bits at 1st and 6th bit, 2nd and 5th bit, 3rd and 4th bit positions.
Hence to check whether bits in different pairs have same value we need to have XNOR gate and then AND them to see whether all pairs satisfy the condition.
So we have the general circuit as next:
We can verify this for a 4-bit number as done next.
So K-map for that is as
And hence we see that we need to XNOR the corresponding bits and then take AND of all outputs of XNORs
Q- Find out the situation when the following circuit of MUX 2 to 1 would not work as expected and how can we eliminate the error.
Ans: When we have the static values at the inputs circuit would work fine but when ever there is a transition in the value of Select pin we have a situation we neither of the two inputs are selected. Following is the truth table for 2 to 1 MUX
SEL(s) Y
0 A
1 B
(a) Suppose we have the SEL = 1, then we have ‘B’ at the output and when we have SEL= 0 we have ‘A’ at the output. But when there is a transition from SEL= 1 to SEL=0 there is problem we face.
When we change SEL from 1 to 0, AND2 deactivates and hence ‘B’ is not passed and as we have a delay of inverter, hence it would take 1 ns extra to activate the AND1 and hence even A is not immediately passed. So we see that neither A nor B is passed to Z for this 1 ns.
(b) Suppose we have the SEL = 0, then we have ‘A’ at the output and when we have SEL= 1 we have ‘B’ at the output. But when there is a transition from SEL= 0 to SEL=1 there is problem we face.
When we change SEL from 0 to 1, then it would take 1 ns extra to deactivate the AND1 and hence input ‘A’ gets passed to OR gate for this 1 ns. Also immediately after the change of SEL pin from 0 to1 we have the AND2 activated hence ‘B’ is also passed to OR gate for this 1 ns. So both the inputs A & B are passed to output for this 1 ns. But after the 1 ns we have correctly only ‘B’ at the output
Hence we see that in both transitions we have error for period of 1 ns
To correct this we can have an extra Buffer in the circuit which has a delay same as that of inverter i.e. 1 ns as shown next.
Q- Now I make a certain change in the required output. The circuit is same as the previous question but it is not required to be AND gate anymore and output required is a HIGH pulse with width of 2 ns as:
Now one has to choose the BLOCK such that we get the above waveform as output of the whole circuit.
Ans: In the previous question we had the 2 inputs of NOR gate as follow:
By modifying the BLOCK we can only change the 2nd I/P and 1st input would remain the same. Now if we analyze the required O/P also given below to see how we need to change the 2nd I/P
And we know that output is NOR of two inputs. And we get a ‘1’ only when we have ‘0’ at both inputs.We need high pulse of width 2 ns so we need that both inputs remain ‘0’ for 2 ns. Hence to get the required O/P we need to insert the extra delay of 2 ns to the 2nd pulse. And I/P pulses would be
As we just have to delay the 2nd pulse by 2 ns so we insert an extra buffer or two extra inverters in the BLOCK as shown on next page:
Q- We are implementing a 3-input AND gate using the following circuit:
We can replace BLOCK with number of (a) Buffers or (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z and the waveforms are as:
Ans: Now if we orally AND all 3 inputs we get that output of the circuit should be a LOW pulse although after a certain delay. So to ensure proper output at the output line F we have to make sure that all the input signals reach the input lines of NOR gate after equal delay.
If there is difference in delays then there would be many unwanted pulses.
We have F’ = X.Y.Z = X.Y + Z’ = INVERT(X AND Y) + INVERT (Z)
F = {INVERT(X AND Y)} NOR {INVERT (Z)}
As we need invert (Z) at input of OR gate. As there is already one inverter, hence while we decide the components for BLOCK we have to make sure that output of the BLOCK is equal to Input of BLOCK.
Also as delay of inputs X & Y is 4+1 = 5 ns
Hence delay for input Z should also be 5 ns but delay of Z = delay (BLOCK) + delay (INVERTER)
As delay of Z=5 ns delay of inverter = 1 ns
Delay (BLOCK) = 5 – 1 = 4 ns
So while designing BLOCK we have to take care of following:
output of the BLOCK is equal to Input of BLOCK
Delay (BLOCK) = 4 ns
Hence we can replace the BLOCK with 2 Buffers (Tp=2ns) as follow:
Also we can design the block as follow: With four inverters so that we have output equal to input and delay = 4 ns as:
Also we can design the block as follow: With 2 inverters and one BUFFER so that we have output equal to input and delay = 4 ns as
And the output waveforms for the above circuit are:
We have F’ = X.Y.Z = X.Y + Z’ = INVERT(X AND Y) + INVERT (Z)
