Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder.

Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is ignored and 000 is fed into register. We have the circuit as:

In the circuit block of 3 FFs is a register with 2 common inputs.

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2^{nd} FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time –clock delay for 2^{nd} FF = 2 + 6 + 5–2 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz

(b) HOLD TIME:

At 1^{st} FF K input & one input of AND gate for J input is given externally which is supposed to be held stable for hold time but the other input is a feedback from 2^{nd} FF and this input changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1^{st} FF. hence hold time condition is satisfied for 1^{st} FF.

At 2nd FF K inputchanges after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17 ns i.e. more than Hold time

one J input (o/p of 1^{st} FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 = 19 ns i.e. more than Hold time

While other input to J through OR gate is a feed back from o/p of 2^{nd} FF and changes only after time T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time (=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is equal to hold time. Hence condition satisfied.

Hence we can also note that HOLD time doesn’t depend upon the clock frequency while SETUP time violation depends upon the clock frequency.

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 nsand delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3 ns & 2 ns respectively.

Ans: The combinational circuit after the 2^{nd} FF doesn’t affect the clock frequency of the circuit as there is no gated component after that circuit. Hence we represent the delays wrt edge of 1^{st} FF as

And the delayed input must reach before the edge reaches 2^{nd} flip-flop

And we know that for 1^{st} FF clock edge can reach anytime as there is direct input available. Hence we get that

Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2^{nd} FF

= 9 + 13 + 5 – 2 = 25 ns

And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges it’s only the delay which has been introduced in the path way of clock signal. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is subtracted which can also be seen from the diagram.

Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.

And the minimum time period to satisfy every condition at every clock edge is 25 ns

Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and delay of other components is T (buf) = 2ns,ï¿½ ï¿½ T (AND) = 4 ns, T (OR) = 4 ns,ï¿½ ï¿½ ï¿½ ï¿½ T (NOT) = 2 ns in the following circuit.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2^{nd} FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time â€“clock delay for 2^{nd} FF = 9 + 6 + 5â€“2 = 18ns Maximum Clock frequency = F max = 1/18 = 5.55 MHz

Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD & Shift or if bit of multiplier is 1 then ADD multiplicand and SHIFT and if bit of multiplier is 0 then ADD zero (or don’t perform ADD but just) SHIFT. We store multiplier in register Q & multiplicand in A and use adder as:

Now I’ll show the contents of shifter at every clock tick if we have to find A* B = 1011 * 0100

Clock tick contents of register Function

1^{st} tick 0 0000 0100 Initial data is stored in register from inputs

2^{nd} tick 0 0000 0100 Result of adder is stored

2^{nd} tick 0 0000 0010 it is shifted towards right

3^{rd} tick 0 0000 0010 Result of adder is stored

3^{rd} tick 0 0000 0001 shifted right again

4^{th} tick 0 1011 0001 firstly result of adder is stored

Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. Also there is problem of clock skew in the system. We also have to identify the pair of registers between which we need to know the value of clock skew.

Assume value of clock skew between required pair of registers.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges. It’s only the clock skew which is going to affect the value of maximum frequency. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

Note: We can easily notice that we need the value of clock skew between only adjacent pair of Flip-flops. We have assumed the value of skew as 3 ns between the pairs.

And the minimum time period to satisfy every condition at every clock edge is 24 ns

Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz

IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while it’s meaningless to know about the cock skew between other pair of flip-flops. Hence in the above case we only need to know the value of clock skew between FF1 & FF2 and FF2 & FF3 while skew between FF1 & FF3 is meaningless.

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2^{nd} FF in the above circuit.

Ans: We firstly represent the delays wrt edge of 1^{st} FF as

And the delayed input must reach before the edge reaches 2^{nd} flip-flop

The clock skew is basically the delay in clock signal reaching 2^{nd} flip-flop. Hence this is quiet similar to the previous question of a buffer in the pathway of clock.

Hence Clock time period is T = T CLK to Q + cdelay + Setup time – Clock Skew

= 9 + 13 + 5 – 3 = 24 ns

And maximum frequency of the circuit is F max = 1 / 24 = 4.16 MHz

It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times.

e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.

CAUSES: There are basically 2 reasons due to which clock skew exists in the system:

Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance.

Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.

Effects of clock skew:

Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1^{st} FF would change (hence input of 2^{nd} FF is changed overriding the previous input) before HOLD time condition for the input of 2^{nd} FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2^{nd} FF change to create SETUP time violations.

Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).

The logic circuit of this type of counters is simple to design and we feed output of one FF to clock of next FF

The circuit diagram for type of counter becomes difficult as number of states increase in the counter

Propagation Time

Propagation time delay of this type of counter is :Tpd = N * (Delay of 1 FF)which is quiet highN is number of FFs

Propagation time delay of this type of counter is:Tpd = (Delay of 1 FF) + delay of 1 gateInclusion of delay of 1 gate would be illustrated when we design higher counters: