Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder. Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is […]

# Sequential Circuits

## Q7: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = […]

## Q6: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of […]

## Q5: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]

## Q4: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and delay of other components is T (buf) = 2ns,ï¿½ ï¿½ T (AND) = 4 ns, T (OR) = 4 ns,ï¿½ ï¿½ ï¿½ ï¿½ T (NOT) = […]

## Q3: Binary Multiplier

Q-Implement binary multiplication using shifter: Eg. If we are multiply 11 * 4 Then 11 = 1011 4 = 0100 Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD […]

## Q2: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]

## Q1: Maximum Frequency

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in […]

## Clock Skew

It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times. e.g. If in the circuit given below, CLK signal reaches the two flip-flops at […]

## Comparison b/w Synchronous & Asynchronous counters

Asynchronous Synchronous Circuit The logic circuit of this type of counters is simple to design and we feed output of one FF to clock of next FF The circuit diagram for type of counter becomes difficult as number of states increase in the counter Propagation Time Propagation time delay of this type of counter […]