Let’s first now derive the D flip-flop from RS flip-flop which we have already done:
We first write the truth table for required D flip-flop as
Now we write the excitation table of given FF SR flip-flop as
Now we need to make a arrangement so that we manipulate input D to inputs R, S such that we get the same output with RS FF as that of D FF. So we combine the two tables given above with same outputs in the same row:
Now we design the combinational circuit to convert D input to SR inputs using K-map as:
Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change.
E.g. As in truth table we say for T flip-flop if input T is 1 and previous Q is 0 then we have output as 1 while in excitation table we are given that present output Q is 0 and new Q is 1 then input T is 1.
Next we write truth table of various flip-flops and then we write their excitation flip-flops.
The truth table of the RS flip-flops is as:
Now to write the excitation table of this flip-flop we first write the various output changes possible as:
Now we can see from that truth table that to change output from 0 to 0, we can keep inputs S, R as 0, 0 or 0, 1 and we can write both the combinations as 0, X which means we just need to keep S=0 and R can have either of two possible values.
Similarly we can note that for output change from 0 to 1, we keep inputs at S=1, R=0.Similarly we can find the other cases and we get the table as:
Similarly we can find out the excitation tables for other kind of flip-flops as shown next:
Theexcitation table of D flip-flop is as:
Theexcitation table of JK flip-flop is as:
For output change from 0 to 1 we can either keep inputs J, K as 1, 0 or we can make use of toggle input combination J=1, K=1 to get compliment of the output.
When R=0, S=0 we don’t have a change in the output in the circuit.
When R=0, S=1 we have output as Q=1 and Q bar = 0
When R=1, S=0 we have the output as Q=0 and Q bar = 1
But when we have R=1, S=1, both R and S make outputs of their NOR gates 0. Hence we have Q=0, Q bar = 0 which is not a valid case as Q & Q bar should be compliment of each other and hence we don’t consider this case. This is called RACE CONDITION. All these cases can be collectively represented in a table as follow:
Let’s draw the timing diagram of the RS latch: t is the delay for a NOR gate.
Initially we have R=0, S=0 and Q=0. When value of S changes to 1, we see in the circuit of RS latch, output of NOR gate (which is Q’) becomes 0 after delay of t ns. Hence both Q & Q’ are 0.Now inputs of other NOR gate become R=0 & Q’=0 and hence we get Q as 1 after another delay of t ns which is shown in the timing diagram. Similarly other outputs are shown.