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## Q3: Binary Multiplier

Q-Implement binary multiplication using shifter:

Eg. If we are multiply 11 * 4

Then 11 = 1011                  4 = 0100

Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD & Shift or if bit of multiplier is 1 then ADD multiplicand and SHIFT and if bit of multiplier is 0 then ADD zero (or don’t perform ADD but just) SHIFT. We store multiplier in register Q & multiplicand in A and use adder as:

Now I’ll show the contents of shifter at every clock tick if we have to find A* B =  1011 * 0100

Clock tick                             contents of register                                        Function

1st tick                                   0              0000       0100                       Initial data is stored in register from inputs

2nd tick                                  0              0000       0100                       Result of adder is stored

2nd tick                                  0              0000       0010                       it is shifted towards right

3rd tick                                   0              0000       0010                       Result of adder is stored

3rd tick                                   0              0000       0001                       shifted right again

4th tick                                   0              1011       0001                       firstly result of adder is stored

4th tick                                   0              0101       1000                       now right shifted

5th tick                                   0              0101       1000                       Result of adder is stored

5th tick                                   0              0010       1100                       Again right shifted

And we get the answer as 001011002

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## Q1: Maximum Frequency

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns     T (hold time) = 4ns             T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in the above circuit.

Ans: We firstly represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

The clock skew is basically the delay in clock signal reaching 2nd flip-flop. Hence this is quiet similar to the previous question of a buffer in the pathway of clock.

Hence Clock time period is T = T CLK to Q + cdelay + Setup time – Clock Skew

= 9 + 13 + 5 – 3 = 24 ns

And maximum frequency of the circuit is F max = 1 / 24 = 4.16 MHz

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## Clock Skew

It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times.

e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.

CAUSES: There are basically 2 reasons due to which clock skew exists in the system:

1. Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance.
2. Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.

Effects of clock skew:

• Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations.
• Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).
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## Synchronous Counter

In synchronous counters we have the same clock signal to all the flip-flops.

MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s

We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & K for 1st FF as 1 and hence output of 1st FF toggles and changes from 0 to 1. But when 1st cock edge had come output of 1st FF was 0. Hence J & K for 2nd FF for 1st edge are 0. So output of this FF doesn’t change and we get Q1=0. so the output is (Q1Q0)2= 012.

On the next edge, output of 1st FF changes from 1 to 0 as J & K are always 1 for this FF. Inputs for 2nd edge for 2nd FF are J=1 & K=1. Hence output changes from 0 to 1. so we get the count as (Q1Q0)2= 102.

Similarly on the next edge we’ll get the output count as (Q1Q0)2= 112.

And on the 4th clock edge both the outputs get reset and we get the output as (Q1Q0)2= 002 and again whole procedure is repeated.

We’ll be studying other synchronous counter when we discuss the design of synchronous circuits later.

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## Glitch

A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop.  e.g.

• We can see in the wave-forms given above for MOD-14 counter that there is a glitch in the Q2 signal which is produced due to delay of AND gate to reset the FF.
• Also a glitch can be generated when we AND two signals and there is a slight delay between two signals. Such a combinational circuit is used when we have to transfer data serially between two registers discussed already and we need limited number of clock cycles for proper working.

The following circuit was designed to produce enable signal (with 4 clock cycles)

But due to slight delay in the one of the input signals there is glitch in the output which would lead to mal-functioning of the circuit.

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## Q: Design custom ripple counter

Q- Design the ripple counter whose output sequence is represented by the following state diagram.

Ans: As we can see that it is a down counter so we’ll be using Q bar of all flip-flops as clock to next flip-flops (negative edged FFs). We draw the table as

Q2         Q1          Q0                          OUTPUT

0              0              0                              0

0              0              1                              0

0              1              0                              1

0              1              1                              1

1              0              0                              1

1              0              1                              1

1              1              0                              1

1              1              1                              1

And using K-map we get the combinational circuit as:

And the equation we get is

Z= Q2 + Q1

And the whole circuit is as:

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## Down Counter (Reverse counting)

Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next flip-flop.

And the output waveform would be as:

Or

And the output waveform would be as:

In both cases we take (Q4 Q3 Q2 Q1) 2 as value of the count

Or

We can just use the same circuit as the UP counter but

Consider the following circuit

And we see that this circuit is a UP counter which count from 0 to 7 and then it is reset but the same circuit can also work as DOWN counter when we take count as combination of inverted outputs for each FF. i.e.. Hence output count of the above circuit would go from 7 to 0 and then again it is set to 7.

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## Q: Design custom ripple counter

Q- Design the ripple counter whose output sequence is represented by the following state diagram.

Ans: As it is a 3-bit counter hence we firstly arrange 3 FFs and now we design the combinational circuit to reset the counter at appropriate point.

Q2         Q1          Q0                          OUTPUT

0              0              0                              0

0              0              1                              1

0              1              0                              1

0              1              1                              1

1              0              0                              1

1              0              1                              1

1              1              0                              1

1              1              1                              0

And using K-map we get the combinational circuit as:

And the equation we get is

Z= Q2. (Q1 bar) + Q0. (Q1bar)

+ Q1. (Q0bar)

= Q2. (Q1 bar) + XOR (Q1, Q0)

OR

We can also have the equation as

Z= Q0. (Q1 bar) + Q1. (Q2bar)

+ Q2. (Q0bar)

And hence can have two types of combinational circuits to achieve the above counter. And the whole circuit with first combinational circuit as:

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## Counter other than MOD-2n

Q-Can we design a ripple counter other than MOD-2n?

Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example:

Design a MOD-14 counter.

First we design a counter of 2’s multiple greater than 14 which is 16. So we first design a MOD-16 counter as:

Now we need to design a combinational circuit which would take care that counter is reset when count value reaches 13. For this we first draw the waveforms as:

As we have to count till 13 and reset again. We see that when-ever Q4=1, Q3=1 & Q1=1, when have to reset the value of all the flip-flops so that we get the value of count as 0. Hence we take NAND of these 3 variables due to which we get a zero when all 3 variables are 1 and output of NAND gate is connected to all the ACTIVE LOW CLEAR lines to reset all flip-flops as follow. We also have to make sure that the output of this NAND gate is zero only after 13.

And now we the output waveforms as:

And we can clearly observe that we have achieved MOD-14 counter as all count values are reset after 13 but in this method we have to observe the output waveforms and then decide the combinational circuit to reset value after certain count.

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## Ripple counter

We can attach more flip-flops to make larger counter. We just use more flip-flops in cascade and give output of first to the clock of 2nd and output of 2nd to clock of 3rd and so on. This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a divide by larger value circuit. Let’s see how we can make larger counters:

And following waveforms would illustrate how the above circuit does counting. It is actually a MOD-8 counter so it would count from 0 to 7 and then again reset itself as shown:

With every negative edge, count is incremented and when the count reaches 7, next edge would reset the value to 0.

These waveforms represent count as (Q3 Q2 Q1) 2.

Hence we can design a MOD-2n counter using n flip-lops in cascade