Q-Implement binary multiplication using shifter: Eg. If we are multiply 11 * 4 Then 11 = 1011 4 = 0100 Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD […]
Tag: clock
Q1: Maximum Frequency
Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in […]
Clock Skew
It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times. e.g. If in the circuit given below, CLK signal reaches the two flip-flops at […]
Synchronous Counter
In synchronous counters we have the same clock signal to all the flip-flops. MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & […]
Glitch
A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop. e.g. We can see in the wave-forms given above for MOD-14 counter that there is a glitch in the Q2 signal […]
Q: Design custom ripple counter
Q- Design the ripple counter whose output sequence is represented by the following state diagram. Ans: As we can see that it is a down counter so we’ll be using Q bar of all flip-flops as clock to next flip-flops (negative edged FFs). We draw the table as Q2 Q1 Q0 OUTPUT 0 0 0 0 […]
Down Counter (Reverse counting)
Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next […]
Q: Design custom ripple counter
Q- Design the ripple counter whose output sequence is represented by the following state diagram. Ans: As it is a 3-bit counter hence we firstly arrange 3 FFs and now we design the combinational circuit to reset the counter at appropriate point. Q2 Q1 Q0 OUTPUT 0 0 0 0 0 0 1 1 0 1 […]
Counter other than MOD-2n
Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example: Design […]
Ripple counter
We can attach more flip-flops to make larger counter. We just use more flip-flops in cascade and give output of first to the clock of 2nd and output of 2nd to clock of 3rd and so on. This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a divide by larger […]