Sequential Circuits

JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]

Sequential Circuits

D Latch

As we have already discussed that when ever we have both R & S equal to 1 we witness an ambiguous state. Hence to avoid this we have made an arrangement in which we’ll never have both R & S equal. We connect the two inputs with an inverter between them as shown below: This […]

Sequential Circuits

Clock

A clock signal is defined by clock period or clock frequency. The clock period is defined as time interval after which clock repeats it self or we can define it as time gap between two consecutive falling edges or two consecutive rising edges and clock frequency is defined as number of clock pulses in a second. Clock […]