Sequential Circuits

Timing Problem in Latches

Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown:

Suppose we have the following circuit:

In this circuit when ever we have E=1, output Q of latch is complimenting again and again as we have connect the Q-bar to D input. We represent the above in waveforms as:

But ideal is that we have only one transition in the output per clock. Hence to avoid this problem we use edge triggered flip-flops.

PROBLEM IN JK & T LATCH: When we have J=1, K=1 or T=1 then output is complimented and if CLK (OR E) is still HIGH, then when the new output is fed back, output is complimented again and this way output is continuously complimented. This problem is called RACE AROUND PROBLEM. We can observe this as:

Let  Q=1,Q’=0 with  J=1, K=1 or T=1, then lower AND gate is enabled and hence J=0, K=1 is passed and output is cleared and we have Q=0, Q’=1. If CLK (OR E) is still HIGH and now as Q=0, Q’=1, then upper AND gate is activated and J=1, K=0 is passed, hence output is now set i.e. Q=1,Q’=0 and so on….

To avoid this RACE AROUND PROBLEM we can make sure that pulse width of the clock is less than the propagation delay of the Latch. Due to this restriction JK & T latches are generally not used in this form but as edge triggered flip-flops which are discussed later.

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