Sequential Circuits

JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow:

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Let’s now try to understand this circuit.

We can see that in the circuit above we have ANDed Q bar with J & CLK (OR E) and Q with K & CLK(OR E). Hence when we have previous Q=1, Q bar=0 then J would not be passed further and K would be passed which means latch can be cleared if we have previous Q=1.

When we have Q=0, Q bar=1 then only K would not be passed and J would be passed and we see that Latch can be set if previous output is 0.

We discuss all the cases below:

When J=1.K=1

If previous Q=0, then we need to get output as Q=1(compliment of previous output), Q bar=0 hence we need to have inputs reaching the basic flip-flop are J=1, K=0. Hence we AND input K with the previous output Q and J with Q bar, due to which only upper AND is activated and only J is passed and hence we get the output=1.

If previous Q=1, then we need to get output as Q=0 (compliment of previous output), Q bar=1. Hence we need inputs to the basic flip-flop as J=0, K=1 to clear the output. As we have ANDed J with previous Q bar and K with Q, lower AND gate is activated and K=1 is passed to clear the output.

When J=1, K=0

As J is ANDed with Q’ so J=1 would be passed only when we have we have Q’=1. Hence when we have Q=0 & Q’=1, upper AND gate is activated and J would be passed further and hence output would be set to 1. And if we have previous outputs as Q=1 & Q’=0, we need not pass J as output would be same even if we pass it.

When J=0, K=1

As K is ANDed with Q, so K=1 would be passed further if we have previous Q=1 & Q’=0 (lower AND gate is activated) and hence output would be cleared but if previous Q=0, Q’=1 then we need not pass the inputs J=0, K=1 (which would clear the output) as they’ll not affect the output independent of whether inputs are passed or not.

When J=0, K=0

As both the inputs are zero, output is not affected.

The following table summarizes all the functioning:

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Waveforms representing the behavior of JK latch are as:

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