## Shift register

In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as: PARALLEL IN PARALLEL OUT: This type of shift registers is already discussed above. SERIAL IN SERIAL OUT: Right shift: Here data is shifted by one bit from left to right with every clock […]

## Registers

A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells. Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse. But […]

## T  Latch

This latch is obtained from JK by connecting both the inputs. This is also known as Toggle latch as output is toggled if T=1. The truth table is: The circuit diagram of T latch is as follow:

## JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]

## Clocking RS latch

We can control RS Latch with clock by ANDing both inputs with clock separately as: Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, […]

## Q1: Timing Diagram

Q- We are implementing a 3-input AND gate using the following circuit: We can replace BLOCK with number of (a) Buffers   or   (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z and the waveforms are as: Ans:  Now if we orally […]

## Logic Gates

Following are the basic logical operations which we can operate on binary variables: AND: This operation is represented by dot (.) If we two binary variables as x and y then we can represent AND operation by z=x.y and resultant of the operations is also a binary variable. Following table represents result of AND of every […]