Q1: Timing Diagram

Q- We are implementing a 3-input AND gate using the following circuit:

We can replace BLOCK with number of (a) Buffers   or   (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z and the waveforms are as:

Ans:  Now if we orally AND all 3 inputs we get that output of the circuit should be a LOW pulse although after a certain delay. So to ensure proper output at the output line F we have to make sure that all the input signals reach the input lines of NOR gate after equal delay.

If there is difference in delays then there would be many unwanted pulses.

We have F’ = X.Y.Z = X.Y + Z’ = INVERT(X AND Y) + INVERT (Z)

F = {INVERT(X AND Y)} NOR {INVERT (Z)}

As we need invert (Z) at input of OR gate. As there is already one inverter, hence while we decide the components for BLOCK we have to make sure that output of the BLOCK is equal to Input of BLOCK.

Also as delay of inputs X & Y is 4+1 = 5 ns

Hence delay for input Z should also be 5 ns but delay of Z = delay (BLOCK) + delay (INVERTER) 

As delay of Z=5 ns            delay of inverter = 1 ns

Delay (BLOCK) = 5 – 1 = 4 ns

So while designing BLOCK we have to take care of following:

• output of the BLOCK is equal to Input of BLOCK
• Delay (BLOCK) = 4 ns

Hence we can replace the BLOCK with 2 Buffers (Tp=2ns) as follow:

Also we can design the block as follow: With four inverters so that we have output equal to input and delay = 4 ns as:

Also we can design the block as follow: With 2 inverters and one BUFFER so that we have output equal to input and delay = 4 ns as

And the output waveforms for the above circuit are:

And we get the required output.