Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder.

Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is ignored and 000 is fed into register. We have the circuit as:

In the circuit block of 3 FFs is a register with 2 common inputs.

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2^{nd} FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time –clock delay for 2^{nd} FF = 2 + 6 + 5–2 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz

(b) HOLD TIME:

At 1^{st} FF K input & one input of AND gate for J input is given externally which is supposed to be held stable for hold time but the other input is a feedback from 2^{nd} FF and this input changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1^{st} FF. hence hold time condition is satisfied for 1^{st} FF.

At 2nd FF K inputchanges after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17 ns i.e. more than Hold time

one J input (o/p of 1^{st} FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 = 19 ns i.e. more than Hold time

While other input to J through OR gate is a feed back from o/p of 2^{nd} FF and changes only after time T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time (=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is equal to hold time. Hence condition satisfied.

Hence we can also note that HOLD time doesn’t depend upon the clock frequency while SETUP time violation depends upon the clock frequency.

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges it’s only the delay which has been introduced in the path way of clock signal. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is subtracted which can also be seen from the diagram.

Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.

And the minimum time period to satisfy every condition at every clock edge is 25 ns

Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz

Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. Also there is problem of clock skew in the system. We also have to identify the pair of registers between which we need to know the value of clock skew.

Assume value of clock skew between required pair of registers.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges. It’s only the clock skew which is going to affect the value of maximum frequency. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:

Note: We can easily notice that we need the value of clock skew between only adjacent pair of Flip-flops. We have assumed the value of skew as 3 ns between the pairs.

And the minimum time period to satisfy every condition at every clock edge is 24 ns

Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz

IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while it’s meaningless to know about the cock skew between other pair of flip-flops. Hence in the above case we only need to know the value of clock skew between FF1 & FF2 and FF2 & FF3 while skew between FF1 & FF3 is meaningless.

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2^{nd} FF in the above circuit.

Ans: We firstly represent the delays wrt edge of 1^{st} FF as

And the delayed input must reach before the edge reaches 2^{nd} flip-flop

The clock skew is basically the delay in clock signal reaching 2^{nd} flip-flop. Hence this is quiet similar to the previous question of a buffer in the pathway of clock.

Hence Clock time period is T = T CLK to Q + cdelay + Setup time – Clock Skew

= 9 + 13 + 5 – 3 = 24 ns

And maximum frequency of the circuit is F max = 1 / 24 = 4.16 MHz

Q- Design MOD-3 ripple counter using (a) Observing outputs (b) K-maps to design the circuit.

Ans: (a)We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 2^{2} and greater than 2. We can see directly that as we have to reset the counter only after 2 i.e. when output is 3 we reset the counter and hence we need to reset only when we have Q0= 1 & Q1=1. Now firstly design MOD-4 counter using 2 FFs and then take NAND of Q0 & Q1 and feed the output to CLEAR of both FFs.

(b) We firstly draw state diagram of the counter required as:

And we have the general circuit to design the other than MOD 2^{ n} then we have the general circuit as

And now we draw a table to list the different input combinations to Combinational circuit and their corresponding output as:

Q1 Q0 OUTPUT of reset logic

0 0 1

0 1 1

1 0 1

1 1 0

And using K-map as

And hence we get the whole circuit for MOD-3 counter as

We can attach more flip-flops to make larger counter. We just use more flip-flops in cascade and give output of first to the clock of 2^{nd} and output of 2^{nd} to clock of 3^{rd} and so on. This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a divide by larger value circuit. Let’s see how we can make larger counters:

And following waveforms would illustrate how the above circuit does counting. It is actually a MOD-8 counter so it would count from 0 to 7 and then again reset itself as shown:

With every negative edge, count is incremented and when the count reaches 7, next edge would reset the value to 0.

These waveforms represent count as (Q3 Q2 Q1)_{ 2}.

Hence we can design a MOD-2^{n} counter using n flip-lops in cascade

This is a special type of register in which 1 moves in the output in the ring i.e. initially output of 1^{st} FF is 1. On next edge this 1 is transferred to output of 2^{nd} FF while previous output becomes 0. Similarly on next clock output of 3^{rd} FF becomes 1. Similarly it continuous till last FF goes 1. After this 1^{st} FF goes 1 goes again and whole procedure is repeated. This way 1 is moved in a ring as:

i.e.

Clock Q_{4} Q_{3} Q_{2} Q_{1}

Initially 0001

1^{st} tick 0010

2^{nd} 0100

3^{rd} 1000

4^{th} 0001

And so on

Hence we use only 4 states out of 16 states possible in Ring counter.

Or we can say there are 12 unused states in Ring counter.

Circuit diagram to achieve Ring Counter is as:

To start the Ring counter, we firstly give START=0 and then rightmost FF is set and all others are reset and hence initial output is 0001

We can also realize Ring counter using JK flip-flop as:

Application: We can use Ring counter in the system where we have to perform different operations sequentially and repeatedly. Suppose we have to do operations A, B, C & D. Firstly we have to do A, then B, then C, and then D. after performing all operations we have to perform operation A and so on. In this case we can use Ring counter to initiate these operations sequentially.

In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as:

PARALLEL IN PARALLEL OUT:

This type of shift registers is already discussed above.

SERIAL IN SERIAL OUT:

Right shift: Here data is shifted by one bit from left to right with every clock tick.

Left shift: Here data is shifted by one bit from right to left with every clock tick

SERIAL IN PARALLEL OUT: In this type of register we firstly load data serially in the register. For a 4-it register we’ll need 4 clock cycles to load data and then output comes out in parallel mode.

PARALLEL IN SERIAL OUT: In this type of shift registers we first input the Parallel data by using LOAD=1 and then data is shifted and data comes out serially.