Sequential Circuits

Q7: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns,   T (AND) = 4 ns, T (OR) = 4 ns,     T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF.

Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns

Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time –clock delay for 2nd FF = 2 + 6 + 5–2 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz

(b) HOLD TIME:

At 1st FF K input & one input of AND gate for J input is given externally which is supposed to be held stable for hold time but the other input is a feedback from 2nd FF and this input changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1st FF. hence hold time condition is satisfied for 1st FF.

At 2nd FF K inputchanges after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17 ns i.e. more than Hold time

 one J input (o/p of 1st FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 = 19 ns i.e. more than Hold time

While other input to J through OR gate is a feed back from o/p of 2nd FF and changes only after time       T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time (=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is equal to hold time. Hence condition satisfied.

Hence we can also note that HOLD time doesn’t depend upon the clock frequency while SETUP time violation depends upon the clock frequency.

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