Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.
Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges it’s only the delay which has been introduced in the path way of clock signal. We represent everything as:
If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:
FF1 Tmin = setup FF1 = 5 ns
FF2 Tmin = T1 CLK to Q + cdelay1 + setup FF2 – clock delay= 9 + 13 + 4 – 2 = 24 ns
FF3 Tmin = T2 CLK to Q + cdelay2 + setup FF3 – clock delay= 7 + 16 + 4 – 2 = 25 ns
As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is subtracted which can also be seen from the diagram.
Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.
And the minimum time period to satisfy every condition at every clock edge is 25 ns
Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz