## Q2: Timing Diagram

Q- Now I make a certain change in the required output. The circuit is same as the previous question but it is not required to be AND gate anymore and output required is a HIGH pulse with width of 2 ns as: Now one has to choose the BLOCK such that we get the above […]

## K-maps for XOR and XNOR gates

Even variable map: For 4 variables (even), we have XOR and XNOR compliment of each other and can be represented in K-maps as follow: For XNOR gate we have 2n/2 number of min terms with output as 1 (i.e. we have even number of 0s) For XOR gate we have 2n/2 number of min terms with […]

## Question 7: ANALYSIS OF NAND CIRCUIT

Q7- We implement the 3-input NAND gate circuit as follow and we are given the gate delay of d ns and 3 inputs are shown as: And give us the output of the circuit and compare it with the ideal output. Ans:  Firstly we NAND of A&B is calculated and then it is inverter to get […]

## Question 5: OUTPUT OF CIRCUIT

Q5- What is the output of the following circuit? Ans:  This circuit may look simple to you as one has to just evaluate every NOR gate and get the final output but I say it is even simpler than this. Let’s analyze the truth table of NOR gate:  And we see that even if only one […]

## Question 4: TIMING DIAGRAM

Q4- Draw the output waveform of the NAND gate when we have the two inputs as follow and delay of the gate is equal to 12.5 ns when output goes from LOW to HIGH and delay is 17.5 ns when output goes from HIGH to LOW. Ans: To get the exact output waveform we firstly draw […]

## Question 3: TIMING DIAGRAM (Diff Units)

Q3- Sometimes delay of gates and the waveforms are given in different units. So let’s take such example with same circuit and delay as above but waveforms as below: Ans: So we convert the delay into ps (Pico seconds) So delay for NOR= 3ns = 3000ps Delay for BUFFER =1ns=1000ps Delay for AND=4ns=4000ps  So the waveforms […]

## Question 2: TIMING DIAGRAM

Q2- Draw the output of the circuit when waveforms of inputs X & Y are as given. Take initial output values as zero. We’ll first calculate output of NOR gate and delay the output by 3ns. Then we draw output of BUFFER with delay of 1ns and finally we take AND of 2 outputs and […]

## Special Characteristics of an IC

A gate IC can be realized using different logic families (explained later) and hence every gate have the following characteristics which may vary with different logic family. The most important parameters are the following Fan-out: It specifies the maximum number of standard gates that output of a gate can rive without affecting its own working. This […]

## Division of the circuit in different levels

We have some eternal inputs which are used directly or indirectly by the elements of the circuit to obtain output. The elements or the gates which receive all their input from the external inputs directly constitute the logical level one of the circuit while the gates which receive at least one input from the output […]

## Question: Implement XOR using NAND only

Q- Implement 2 variable XOR gate using NAND only in minimum number of gates. F= x XOR y = x’y+xy’ = x’y+xy’+xx’+yy’ = (x+y) (x’+y’) Now we need to implement this circuit using NAND gates F= (x+y)(xy)’ = x. (xy)’ + y. (xy)’ Take compliment F’= ( x. (xy)’ + y. (xy)’ )’ = (x. […]