Combinational Circuits

Q2: Timing Diagram

Q- Now I make a certain change in the required output. The circuit is same as the previous question but it is not required to be AND gate anymore and output required is a HIGH pulse with width of 2 ns as:

Now one has to choose the BLOCK such that we get the above waveform as output of the whole circuit.

Ans: In the previous question we had the 2 inputs of NOR gate as follow:

By modifying the BLOCK we can only change the 2nd I/P and 1st input would remain the same. Now if we analyze the required O/P also given below to see how we need to change the 2nd I/P 

And we know that output is NOR of two inputs. And we get a ‘1’ only when we have ‘0’ at both inputs.We need high pulse of width 2 ns so we need that both inputs remain ‘0’ for 2 ns. Hence to get the required O/P we need to insert the extra delay of 2 ns to the 2nd pulse. And I/P pulses would be

As we just have to delay the 2nd pulse by 2 ns so we insert an extra buffer or two extra inverters in the BLOCK as shown on next page:

 Or

Or

Or

etc.

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