## Master slave Flip flop

We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level.  Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]

## T  Latch

This latch is obtained from JK by connecting both the inputs. This is also known as Toggle latch as output is toggled if T=1. The truth table is: The circuit diagram of T latch is as follow:

## JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]

## Clocking RS latch

We can control RS Latch with clock by ANDing both inputs with clock separately as: Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, […]

## Deriving the circuit of Flip flop

DERIVING THE CIRCUIT OF FLIPFLOP (from digital components): To understand the logic let’s consider a basic circuit of an inverter with a feedback as below: Now what would be the output of the circuit?  We know what ever is at input, we’ll get inverse of that at output and as output is fed back to input […]

## Question: Implement XNOR gate using NOR only

Q- Implement 2 variable XNOR gate using NOR only in minimum number of gates. F= x XNOR y = (x XOR y)’ F’= (x XOR y) = x’y+xy’ = x’y+xy’+xx’+yy’ = (x+y) (x’+y’) F’= x’(x+y) + y’(x+y) Take compliment F= (x’(x+y) + y’(x+y))’ = (x’(x+y) )’ . (y’(x+y))’ =(x+(x+y)’). (y + (x+y)’)   Take compliment again […]

## Universal Gates

NAND and NOR gates are called universal gates as any digital function can be implemented by using only NAND or NOR gate alone. Combinational and sequential both type of circuits can be implemented using NAND or NOR gate. Let’s see how we can derive all basic gates from NAND: Let’s now see that how we […]