Sequential Circuits

Master slave Flip flop

We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level. 

Diagram of the RS master-slave flip-flop is as:

First latch acts as a master and 2nd latch acts as a slave. Master latch is enabled on positive level and slave latch is enabled on negative level. Hence when ever CLK goes positive, master latch starts accepting the inputs and generates the outputs correspondingly. But as slave latch is disabled it accepts none of the generated outputs but when CLK goes LOW, 2nd latch starts accepting inputs and inputs are actually the final output of the master latch (which is the output corresponding to the inputs at last moments of HIGH pulse to master latch just before falling edge) . Hence slave latch just passes that final output of the master latch to the output terminals or we can say as a whole, output is produced only corresponding to the inputs which are just before the falling edge and the whole circuit acts as a negative edged flip-flop.

Circuit diagram of RS master-slave is as:

Similarly we can achieve a positive edged flip-flop by triggering master flip-flop on negative level and slave flip-flop on positive level of the pulse. We’ll use inverter to master flip-flop instead of slave flip-flop.

We can have a Master-Slave JK flip-flop as following diagram:

And while drawing the circuit diagram we instead of giving two feed backs (one for each flip-flop), we’ll draw only a single feedback from the final output of the whole circuit to the input of the circuit and implement the JK flip-flop. We can analyze the circuit as we did in case JK latch and see that JK flip-flop is implemented by following circuit:

-: Master Slave JK flip-flop:-

Following waveforms for positive edge triggered flip-flop would further illustrate the working of an edge triggered flip-flops:

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