Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of […]
Tag: D flip flop
Q5: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]
Q2: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]
Clock Skew
It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times. e.g. If in the circuit given below, CLK signal reaches the two flip-flops at […]
Johnson Counter
While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we connect Q bar of last to D of 1st FF as shown below and we also don’t need to connect preset of 1st FF. This is also called Twisted Ring counter: And JK implementation is as follow: And we have […]
Shift register
In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as: PARALLEL IN PARALLEL OUT: This type of shift registers is already discussed above. SERIAL IN SERIAL OUT: Right shift: Here data is shifted by one bit from left to right with every clock […]
Registers
A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells. Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse. But […]
Conversion: D to T & T to D FF
Similar to previous conversions, we get the circuits as follow: D FF to T FF: T FF to D FF: Note: We have not shown the clock but we can attach the clock signal to the given FF. Similarly we can obtain other conversions.
Conversion: D to RS flip-flop
We first write the truth table for required Flip-flop i.e. RS FF Now we write the excitation table of given FF i.e. D flip-flop as Now we combine two tables to get the combinational circuit as: Now we design the combinational circuit to convert J, K to corresponding R, S K-map for D input: And […]
Conversion: RS to D flip-flop
Let’s first now derive the D flip-flop from RS flip-flop which we have already done: We first write the truth table for required D flip-flop as Now we write the excitation table of given FF SR flip-flop as Now we need to make a arrangement so that we manipulate input D to inputs R, S […]