Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3 ns & 2 ns respectively.
Ans: The combinational circuit after the 2nd FF doesn’t affect the clock frequency of the circuit as there is no gated component after that circuit. Hence we represent the delays wrt edge of 1st FF as
And the delayed input must reach before the edge reaches 2nd flip-flop
And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that
Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF
= 9 + 13 + 5 – 2 = 25 ns
And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz