Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 nsand delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3 ns & 2 ns respectively.
Ans: The combinational circuit after the 2nd FF doesn’t affect the clock frequency of the circuit as there is no gated component after that circuit. Hence we represent the delays wrt edge of 1st FF as
And the delayed input must reach before the edge reaches 2nd flip-flop
And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that
Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF
= 9 + 13 + 5 – 2 = 25 ns
And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz
Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.
Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges it’s only the delay which has been introduced in the path way of clock signal. We represent everything as:
If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:
As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is subtracted which can also be seen from the diagram.
Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.
And the minimum time period to satisfy every condition at every clock edge is 25 ns
Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz
Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. Also there is problem of clock skew in the system. We also have to identify the pair of registers between which we need to know the value of clock skew.
Assume value of clock skew between required pair of registers.
Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges. It’s only the clock skew which is going to affect the value of maximum frequency. We represent everything as:
If now we calculate the minimum time period required considering condition at all FF as follow, we’ll find:
Note: We can easily notice that we need the value of clock skew between only adjacent pair of Flip-flops. We have assumed the value of skew as 3 ns between the pairs.
And the minimum time period to satisfy every condition at every clock edge is 24 ns
Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz
IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while it’s meaningless to know about the cock skew between other pair of flip-flops. Hence in the above case we only need to know the value of clock skew between FF1 & FF2 and FF2 & FF3 while skew between FF1 & FF3 is meaningless.
It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times.
e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.
CAUSES: There are basically 2 reasons due to which clock skew exists in the system:
Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance.
Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.
Effects of clock skew:
Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations.
Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).
While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we connect Q bar of last to D of 1st FF as shown below and we also don’t need to connect preset of 1st FF. This is also called Twisted Ring counter:
And JK implementation is as follow:
And we have outputshas follow:
Clock Q4 Q3 Q2 Q1
Initially 0000
1st tick 0001
2nd 0011
3rd 0111
4th 1111
5th 1110
6th 1100
7th 1000
8th 0000
We can also note that we use only 8 out of 16 possible states and in general we have used 2n states and hence we have 2n-2n unused states
In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as:
PARALLEL IN PARALLEL OUT:
This type of shift registers is already discussed above.
SERIAL IN SERIAL OUT:
Right shift: Here data is shifted by one bit from left to right with every clock tick.
Left shift: Here data is shifted by one bit from right to left with every clock tick
SERIAL IN PARALLEL OUT: In this type of register we firstly load data serially in the register. For a 4-it register we’ll need 4 clock cycles to load data and then output comes out in parallel mode.
PARALLEL IN SERIAL OUT: In this type of shift registers we first input the Parallel data by using LOAD=1 and then data is shifted and data comes out serially.
A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells.
Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse.
But in this circuit we have to maintain the inputs to keep the outputs unchanged as we don’t have the input condition in D Flip-flop for unchanged output. Hence we modify the above circuit with an extra
input LOAD which when ‘1’ would mean there is a new input data to be stored and LOAD=0 would mean we have keep the stored data same. The modified circuit is as:
Let’s first now derive the D flip-flop from RS flip-flop which we have already done:
We first write the truth table for required D flip-flop as
Now we write the excitation table of given FF SR flip-flop as
Now we need to make a arrangement so that we manipulate input D to inputs R, S such that we get the same output with RS FF as that of D FF. So we combine the two tables given above with same outputs in the same row:
Now we design the combinational circuit to convert D input to SR inputs using K-map as:
