Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = […]

# Tag: gates

## Counter other than MOD-2n

Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example: Design […]

## Q: Serial Data Transfer

Q- Design a circuit to transfer data serially from one shift register to other. Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not […]

## Shift register

In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as: PARALLEL IN PARALLEL OUT: This type of shift registers is already discussed above. SERIAL IN SERIAL OUT: Right shift: Here data is shifted by one bit from left to right with every clock […]

## Registers

A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells. Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse. But […]

## QUESTIONS: Flip flops/Latch

Q-What is the difference between LATCH & FLIP-Flop? Ans: We can easily find the answer after going through the theory given: Latches are level sensitive while flip-flops are edge sensitive devices Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops. As we can see from different circuits given […]

## T Latch

This latch is obtained from JK by connecting both the inputs. This is also known as Toggle latch as output is toggled if T=1. The truth table is: The circuit diagram of T latch is as follow:

## JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]

## RS Flip flop implementation(NAND gates)

We can also represent the above circuit using NAND gates as: Let’s convert to NAND circuit step by step. R’S’ FLIPFLOP The characteristics of the FF are as given in table: Now we replace R by R (bar) and S by S (bar) and eliminating the 2 circles and hence final circuit.

## Deriving the circuit of Flip flop

DERIVING THE CIRCUIT OF FLIPFLOP (from digital components): To understand the logic let’s consider a basic circuit of an inverter with a feedback as below: Now what would be the output of the circuit? We know what ever is at input, we’ll get inverse of that at output and as output is fed back to input […]