We generally have a standard memory chip available and we have to inter-connect several chips to obtain the specification of memory required for our system design. Suppose we have the following standard chip available:
As it is a chip of 1024 (210) words with each word of 4 bits, so we require 10 address lines to access each word and 4 data lines which are bidirectional lines. We also have two control signals WR bar and CS bar, WR bar is an active low control signal to select whether we’ll writing data into RAM or reading data out of RAM while CS bar is an active low signal, used to select the memory chip. So whenever CS bar is low chip is selected and if CS bar is high then device is disabled and chip reduces its power requirements.
If we require a memory chip of size M * N and we have a standard memory of m * n, then
No. of standard chips required= (M * N) / (m * n)
Q- If we require a memory of 1K * 8 bits then show the arrangement using the chip given above to achieve the configuration needed.
Ans: As we need to increase the width of data lines we’ll connect the two chips horizontally with the same address lone and control feeding the both memory chips and concatenate the data lines of two as shown:
No. of standard chips required= (1024 * 8) / (1024 * 4) = 2
Q- If we require a memory of 4K * 4 bits then show the arrangement using the chip given above to achieve the configuration needed.
Ans: In this case we need to increase theaddressable capability so we’ll arrange the chip in vertical with address lines A0 – A9 are common while A10 – A11 are used to select the chip as shown below :
No. of standard chips required= (4096 * 4) / (1024 * 4) = 4
00 0000000000 to 00 1111111111 is address range of chip at bottom
01 0000000000 to 01 1111111111 is address range of chip 2nd from bottom
10 0000000000 to 10 1111111111 is address range of chip 3rd from bottom
11 0000000000 to 11 1111111111 is address range of topmost chip