Latches which are activated by the edge of the clock are called Flip-flops. If it is a positive edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the clock and if it is a negative edged flip-flop then inputs are accepted only when there is a HIGH to LOW transition in the clock […]
Tag: clock
Parameters of clock pulses
Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some minimum values for proper operation of every flip-flop. This width is measured between 50% transition points of rising and trailing edges of the given signal. Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the […]
Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two […]
Timing Problem in Latches
Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown: Suppose we have the following circuit: In this circuit when […]
JK Latch
This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]
D Latch
As we have already discussed that when ever we have both R & S equal to 1 we witness an ambiguous state. Hence to avoid this we have made an arrangement in which we’ll never have both R & S equal. We connect the two inputs with an inverter between them as shown below: This […]
Clocking RS latch
We can control RS Latch with clock by ANDing both inputs with clock separately as: Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, […]
Deriving the circuit of Flip flop
DERIVING THE CIRCUIT OF FLIPFLOP (from digital components): To understand the logic let’s consider a basic circuit of an inverter with a feedback as below: Now what would be the output of the circuit? We know what ever is at input, we’ll get inverse of that at output and as output is fed back to input […]
Clock
A clock signal is defined by clock period or clock frequency. The clock period is defined as time interval after which clock repeats it self or we can define it as time gap between two consecutive falling edges or two consecutive rising edges and clock frequency is defined as number of clock pulses in a second. Clock […]
CLOCK FREQUENCY
Q- What does a clock frequency mean which is mentioned in a processor configuration e.g. 1.7GHz processor? Ans: This clock frequency is the max clock frequency at which a processor can run. An instruction takes a fixed amount of clock cycles to execute a particular instruction. So higher is the clock frequency and lesser is the clock […]