## Q7: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns,   T (AND) = 4 ns, T (OR) = 4 ns,     T (NOT) = […]

## Excitation table of Flip flops

Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change. E.g. As in truth table we say for T […]

## Characteristics Equation of Flip flops

RS Flip flops: The truth table for RS Flip-flop is as follow: Now let’s draw the K-map and get the equation for output Q. As the Qp and Qp bar are compliment of each other so we’ll consider only one of those in K-MAP D FLIP-FLOP: Truth table is as: The equation we get is JK FLIP-FLOP: The truth […]

## Master slave Flip flop

We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level.  Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]

## Timing Problem in Latches

Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown: Suppose we have the following circuit: In this circuit when […]

## JK Latch

This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]