This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]
Tag: timing diagram
Clocking RS latch
We can control RS Latch with clock by ANDing both inputs with clock separately as: Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, […]
RS Flip flop
When R=0, S=0 we don’t have a change in the output in the circuit. When R=0, S=1 we have output as Q=1 and Q bar = 0 When R=1, S=0 we have the output as Q=0 and Q bar = 1 But when we have R=1, S=1, both R and S make outputs of their […]
Q2: Timing Diagram
Q- Now I make a certain change in the required output. The circuit is same as the previous question but it is not required to be AND gate anymore and output required is a HIGH pulse with width of 2 ns as: Now one has to choose the BLOCK such that we get the above […]
Q1: Timing Diagram
Q- We are implementing a 3-input AND gate using the following circuit: We can replace BLOCK with number of (a) Buffers or (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z and the waveforms are as: Ans: Now if we orally […]
Question 4: TIMING DIAGRAM
Q4- Draw the output waveform of the NAND gate when we have the two inputs as follow and delay of the gate is equal to 12.5 ns when output goes from LOW to HIGH and delay is 17.5 ns when output goes from HIGH to LOW. Ans: To get the exact output waveform we firstly draw […]
Question 3: TIMING DIAGRAM (Diff Units)
Q3- Sometimes delay of gates and the waveforms are given in different units. So let’s take such example with same circuit and delay as above but waveforms as below: Ans: So we convert the delay into ps (Pico seconds) So delay for NOR= 3ns = 3000ps Delay for BUFFER =1ns=1000ps Delay for AND=4ns=4000ps So the waveforms […]
Question 2: TIMING DIAGRAM
Q2- Draw the output of the circuit when waveforms of inputs X & Y are as given. Take initial output values as zero. We’ll first calculate output of NOR gate and delay the output by 3ns. Then we draw output of BUFFER with delay of 1ns and finally we take AND of 2 outputs and […]
Question 1: TIMING DIAGRAM
Q-1 Show the level transitions in the input signal at the output line if Tp1 = 2ns, Tp2 = 2, Tp3=3ns, Tp4= 2 ns and assuming that all the transitions in input occur at t=0 Ans: At node A: We have transition after the delay of Tp1 = 2 ns and at t=2 a HIGH to […]