Q- Can we implement 4 to 1 MUX using (a) three 2 to 1 MUX (b) only two 2 to 1 MUX and a OR gate & NOT gate? Ans: (a) We can implement 4 to 1 MUX from 2 to 1 MUX as shown below: (b) We have already implemented 8 to 1 MUX using […]
Tag: questions
Q8: Implement function using MUX & ADDER
Q- Design and implement the following logical functions with a combinational circuit (with A and B being 4-bit numbers): S1 S0 Output 0 0 A OR B 0 1 A AND B 1 0 A’ 1 1 A XOR B Ans: The following circuit would give the required outputs:
Q7: Implement function using MUX & ADDER
Q- Design and implement the following with a combinational circuit (with A and B being 4-bit numbers): S2 S1 S0 Output 0 0 0 2A 0 0 1 A plus B 0 1 0 A plus B’ 0 1 1 A minus 1 1 0 0 2A + 1 1 0 1 A plus B […]
Q6: Implement function using MUX & ADDER
Q- Design and implement the following with a combinational circuit (with A and B being 4-bit numbers): S1 S0 Output 0 0 A plus B 0 1 left shift A 1 0 A plus B plus 1 1 1 2A + 1 Ans: We need one 4-bit parallel ADDER and MUX to implement the above. As […]
Q5: Implement PALINDROME circuit
Q- Draw the circuit to check a PALINDROME number of even bits. Ans: Palindrome number (in bits) is the number which is same whether seen from the first and the last bit. E.g. 1001, 0110, 0000, 1111 in 4 bits So to check this we need to have same value of bit at 1st bit and […]
Q4: Debug error in MUX
Q- Find out the situation when the following circuit of MUX 2 to 1 would not work as expected and how can we eliminate the error. Ans: When we have the static values at the inputs circuit would work fine but when ever there is a transition in the value of Select pin we have a situation […]
Q3: Implement equations using Half Adders
Q- Implement the following equations using only Half Adder circuits. D= A XOR B XOR C E = A’BC + AB’C F = ABC’ + (A’+B’) C G= ABC Ans: We know the equations for Half Adder are S = A xor B and C = AB And can be represented as follow: We have […]
Q1: Timing Diagram
Q- We are implementing a 3-input AND gate using the following circuit: We can replace BLOCK with number of (a) Buffers or (b) Inverters. The delay of buffer is Tp=2ns. Now we need to choose components such that we have proper output at F= X.Y.Z and the waveforms are as: Ans: Now if we orally […]
PARITY GENERATOR (4-bit MESSAGE)
Q-Implement the parity generator (a) Even (b) Odd for 4-bit message Ans: (a) Following is the truth table and K-map for even parity Binary number Parity (even) 0000 0 0001 1 0010 1 0011 0 0100 1 0101 0 0110 0 0111 1 1000 1 1001 0 1010 […]
Q: Implement LOGIC GATES using MUX
Q- Using 2 to 1 MUX implement the following 2-input gates: (a) OR (b) AND (c) NOR (d) NAND (e) XOR (f) XNOR (g) NOT. Ans: To implement the above for every gate, either we can derive the different gates using the logic (the truth table) or the procedure to implement any function with MUX (discussed […]