Q- Using 2 to 1 MUX implement the following 2-input gates: (a) OR (b) AND (c) NOR (d) NAND (e) XOR (f) XNOR (g) NOT.
Ans: To implement the above for every gate, either we can derive the different gates using the logic (the truth table) or the procedure to implement any function with MUX (discussed earlier)
So from above discussion we can derive the circuit as below:
USING PROCEDURE TO IMPLEMENT ANY FUNCTION USING MUX:
Equation for the OR gate is Z= X+Y
We now convert the above equation into canonical form
Z= X (Y+Y’) + Y (X+X’) = XY + XY’ + YX + YX’ = XY’ + X’Y + XY= F (1, 2, 3)
We take X as the select line
Now write the min terms with Y’ (compliment) and then Y (un-complimented) as follow:
Hence we get that input at line 0 is Y and at line 1 is ‘1’ and we get the circuit same as above.
(b) AND: Similar to the case of OR gate we can derive the circuit for AND gate as below: