Q- Design a circuit to transfer data serially from one shift register to other. Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not […]
Tag: clock
Johnson Counter
While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we connect Q bar of last to D of 1st FF as shown below and we also don’t need to connect preset of 1st FF. This is also called Twisted Ring counter: And JK implementation is as follow: And we have […]
Ring counter
This is a special type of register in which 1 moves in the output in the ring i.e. initially output of 1st FF is 1. On next edge this 1 is transferred to output of 2nd FF while previous output becomes 0. Similarly on next clock output of 3rd FF becomes 1. Similarly it continuous till last FF […]
Shift register
In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as: PARALLEL IN PARALLEL OUT: This type of shift registers is already discussed above. SERIAL IN SERIAL OUT: Right shift: Here data is shifted by one bit from left to right with every clock […]
Q3: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Ans: There is […]
Q2: Maximum frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns Ans: As input to first flip-flop is directly available and […]
Maximum Frequency of the clock signal
To achieve the maximum frequency of the clock signal we can assume to start SETUP time immediately after the CLK to Q delay is finished. This would mean that we can have the next positive edge (CLK to Q delay + SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge […]
Timing parameters of a flip flop
There are basically 3 types of factors which affect the working of a flip flop: 1. Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If […]
Problem in Master Slave
We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs And we see that at the 4th and 5th edge we have the wrong transitions. Why so? Before […]
Master slave Flip flop
We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level. Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]