Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns.
Ans: There is a change in the circuit from the previous questions that we have an extra buffer in the way of clock signal to 2nd flip-flop. Due to this buffer, clock edge reaching 2nd flip-flop delays by 2 ns. Note that we calculate the various delays for input of 2nd FF wrt the clock edge of 1st flip-flop. And input going through all the delays should reach before clock edge reaches the 2nd flip-flop. Let me represent the above in a diagram as follow:
We firstly represent the delays wrt edge of 1st FF as
And the delayed input must reach before the edge reaches 2nd flip-flop
And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that
Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF
= 9 + 13 + 5 – 2 = 25 ns
And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz